Pll Signals; Tap Signals - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

6.8

PLL Signals

Table 6-10. PLL Signals
Signal Name
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
6.9

TAP Signals

Table 6-11. TAP Signals
Signal Name
BPM#[7:0]
BCLK_ITP
BCLK_ITP#
DBR#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
82
Differential bus clock input to the processor
Embedded Display Port PLL Differential Clock In: 120 MHz.
Description
Breakpoint and Performance Monitor Signals: These signals are
outputs from the processor that indicate the status of breakpoints
and programmable counters used for monitoring processor
performance.
These pins are connected in parallel to the top side debug probe to
enable debug capacities.
DBR# is used only in systems where no debug port is implemented
on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
PREQ# is used by debug tools to request debug operation of the
processor.
TCK (Test Clock): This signal provides the clock input for the
processor Test Bus (also known as the Test Access Port). TCK must be
driven low or allowed to float during power on Reset.
TDI (Test Data In): This signal transfers serial test data into the
processor. TDI provides the serial input needed for JTAG specification
support.
TDO (Test Data Out): This signal transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
TMS (Test Mode Select): A JTAG specification support signal used by
debug tools.
TRST# (Test Reset): This signal resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
Description
Signal Description
Direction/
Buffer Type
I
Diff Clk
I
Diff Clk
Direction/
Buffer Type
I/O
CMOS
I
O
O
Asynchronous
CMOS
I
Asynchronous
CMOS
I
CMOS
I
CMOS
O
Open Drain
I
CMOS
I
CMOS
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