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2.8.3
PCICMD2—PCI Command Register
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
130
0/2/0/PCI
4–5h
0000h
RW, RO
16 bits
00h
Reset
RST/
Attr
Value
PWR
RO
0h
FLR,
RW
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
RO
0b
Uncore
FLR,
RW
0b
Uncore
FLR,
RW
0b
Uncore
FLR,
RW
0b
Uncore
Processor Configuration Registers
Description
Reserved
Interrupt Disable (INTDIS)
This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
messages will not be sent to DMI.
Fast Back-to-Back (FB2B)
Not Implemented. Hardwired to 0.
SERR Enable (SERRE)
Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP)
Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE)
Not Implemented. Hardwired to 0. Since the IGD belongs to the
category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error
that it detects and continues with normal operation.
Video Palette Snooping (VPS)
This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE)
Hardwired to 0. The IGD does not support memory write and
invalidate commands.
Special Cycle Enable (SCE)
This bit is hardwired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME)
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
Memory Access Enable (MAE)
This bit controls the IGD's response to memory space accesses.
0 = Disable.
1 = Enable.
I/O Access Enable (IOAE)
This bit controls the IGD's response to I/O space accesses.
0 = Disable.
1 = Enable.
Datasheet, Volume 2
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