Bga1224 Ballmap (Top View, Upper-Right Quadrant) - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Figure 8-6.
35 34 33 32 31 30 29
SB_MA[
RSVD VSS VDDQ
11]
SB_CK SB_MA[ SB_MA[
RSVD
#[0] 1] 8]
SB_MA[
RSVD VDDQ VSS
7]
SB_CK[ SB_MA[ SB_MA[
RSVD
0] 0] 9]
SB_MA[
VSS RSVD VSS
15]
VSS RSVD VDDQ RSVD
SB_MA[
VSS RSVD VSS
3]
SB_MA[ SA_CK[ SB_MA[
VDDQ
5] 0] 14]
SA_CK SA_MA[
VSS VSS
#[0]
SA_CK SB_BS[
VDDQ VDDQ
#[1] 2]
SA_CK[ SB_MA[
VSS VSS
1] 12]
VDDQ VSS VDDQ
VSS VDDQ VDDQ VSS
VDDQ VSS VDDQ
VSS VDDQ VDDQ VSS
VDDQ VSS VDDQ
VSS VDDQ VDDQ VSS
VDDQ VSS VDDQ
124

BGA1224 Ballmap (Top View, Upper-Right Quadrant)

28 27 26 25 24 23 22 21
SB_CKE
VSS RSVD
[1]
SB_MA[
RSVD RSVD RSVD
6]
RSVD VSS RSVD
SB_MA[
RSVD RSVD RSVD
4]
SM_DR
VSS AMRST VSS
#
SA_MA[ SB_CKE SA_MA[
VDDQ
0] [0] 7]
SA_MA[
VSS VSS
8]
SA_MA[ SA_MA[ SA_MA[
RSVD
2] 4] 9]
SA_MA[
VSS VSS
1] 5]
SM_DR
SA_MA[
VDDQ AMPWR VDDQ
6]
OK
SA_MA[ SA_MA[
VSS
3] 11]
VCCPQ
VDDQ VSS VCCDQ
E
VDDQ VDDQ VSS
VCCPQ
VDDQ VSS VCCDQ
E
VDDQ VDDQ VSS
VCCPQ
VDDQ VSS VCCDQ
E
VDDQ VDDQ VSS
VCCPQ
VDDQ VSS VCCDQ
E
20 19 18 17 16 15 14
SB_DQ[ SB_DQ[
VSS VSS
27] 24]
SB_DQ[ SB_DQ SB_DQ[
RSVD
30] S[3]
SB_DQ[ SB_DQ[
VSS VSS
31] 25]
SB_DQ[ SB_DQ SB_DQ[
RSVD
26] S#[3]
SA_MA[
VSS RSVD VSS
14]
SA_CKE
RSVD RSVD
[1]
SA_CKE
VSS VSS RSVD
[0]
SA_BS[
RSVD RSVD
2]
SA_MA[
VSS RSVD VSS
12]
VDDQ_
RSVD RSVD
SENSE
VSS_SE
SA_MA[
NSE_V VSS RSVD
15]
DDQ
VSS VCCIO VCCIO
VCCIO VCCIO VSS VSS
VSS VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO
VSS VSS VSS
VCCIO VCCIO VCCIO VCCIO
VSS VCCIO VCCIO
VSS VSS
VCCIO VCCIO
VCCIO VCCIO
VSS VSS
VCCIO VCCIO
VCCIO VCCIO
VSS VSS
Processor Pin and Signal Information
13 12 11 10 9 8 7
SB_DQ[ VSS_N
VSS VSS
19] CTF
SB_DQ[ SB_DQ SB_DQ[
29] 22] S#[2] 21]
SB_DQ[ SA_DQ[
VSS VSS
23] 18]
SB_DQ[ SB_DQ SB_DQ[
28] 18] S[2] 17]
SA_DQ[ SA_DQ[
VSS RSVD
31] 28]
SA_DQ[ SA_DQ
RSVD VSS
30] S#[3]
SA_DQ SA_DQ[ SA_DQ
VSS
S[3] 22] S#[2]
SA_DQ[ SA_DQ[
RSVD VSS
26] 21]
SA_DQ[ SA_DQ[ SA_DQ[ SA_DQ[
27] 29] 17] 16]
SA_DQ[
RSVD VSS VSS
19]
SA_DQ[ VCCIO_ SA_DQ[ SA_DQ[
24] SENSE 20] 14]
SA_DQ[ SA_DQ[
VCCIO VSS
25] 10]
VSS_SE
SA_DQ SA_DQ
NSE_V
S[1] S#[1]
CCIO
SA_DQ[
VCCIO VSS VSS
15]
SA_DQ[ SA_DQ[ SA_DQ[
8] 9] 13]
SA_DQ[
VSS VSS VSS
2]
SA_DQ[ SA_DQ SA_DQ
6] S#[0] S[0]
SA_DQ[
VCCIO VSS
7]
SA_DQ[ SA_DQ[ SA_DQ[
VCCIO
5] 1]
SA_DQ[
VSS VSS
4]
VCCIO_
VCCIO RSVD RSVD
SEL
PROC_
VCCIO SELECT VSS
#
VCCSA eDP_TX eDP_TX
VSS
_VID[1] [3] #[3]
eDP_TX
VSS VSS
[2]
VCCSA eDP_H eDP_TX
VCCIO
_VID[0] PD #[2]
FDI_IN
VCCIO VSS
T
Datasheet, Volume 1
6 5 4 3 2 1
DC_TES DC_TES
BJ
T_BJ4 T_BJ2
VSS_N DC_TES DC_TES
BH
CTF T_BH3 T_BH1
DC_TES
RSVD
BG
T_BG2
DC_TES
VSS RSVD
BF
T_BF1
SA_DQ[ VSS_N
BE
23] CTF
SA_DQ VSS_N
VSS
BD
S[2] CTF
SB_DQ[ SB_DQ[
BC
20] 16]
SB_DQ[ SB_DQ[
VSS
BB
15] 11]
SB_DQ[ SB_DQ[
BA
10] 14]
SA_DQ[
VSS VSS
AY
11]
SB_DQ SB_DQ
AW
S[1] S#[1]
SB_DQ[ SB_DQ[
VSS
AV
8] 12]
SB_DQ[ SB_DQ[
AU
9] 13]
SA_DQ[
VSS VSS
AT
12]
SB_DQ[ SB_DQ[
AR
7] 3]
SB_DQ[ SB_DQ[
VSS
AP
2] 6]
SB_DQ SB_DQ
AN
S#[0] S[0]
SA_DQ[
VSS VSS AM
3]
SB_DQ[ SB_DQ[
AL
0] 0] 4]
SB_DQ[ SB_DQ[
VSS
AK
1] 5]
DPLL_R
DPLL_R
EF_CLK
AJ
EF_CLK
#
RSVD VSS VSS
AH
eDP_TX eDP_TX
AG
[0] #[0]
eDP_TX eDP_TX
VSS
AF
[1] #[1]
eDP_A eDP_A
AE
UX UX#
RSVD VSS VSS
AD