Dmivc1Rsts-Dmi Vc1 Resource Status Register; Dmivcprcap-Dmi Vcp Resource Capability Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

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2.12.10
DMIVC1RSTS—DMI VC1 Resource Status Register
This register reports the Virtual Channel specific status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:2
1
0
2.12.11
DMIVCPRCAP—DMI VCp Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:24
23:23
22:16
15
14:8
7:0
192
0/0/0/DMIBAR
26–27h
0002h
RO-V
16 bits
0000h
Reset
RST/
Attr
Value
PWR
RO
0h
RO-V
1b
Uncore
RO
0h
0/0/0/DMIBAR
28–2Bh
00000001h
RO
32 bits
00h
Reset
RST/
Attr
Value
PWR
RO
00h
Uncore
RO
0h
RO
00h
Uncore
RO
0b
Uncore
RO
0h
RO
01h
Uncore
Processor Configuration Registers
Description
Reserved
Virtual Channel 1 Negotiation Pending (VC1NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
Software may use this bit when enabling or disabling the VC. This
bit indicates the status of the process of Flow Control initialization.
It is set by default on Reset, as well as when the corresponding
Virtual Channel is Disabled or the Link is in the DL_Down state. It
is cleared when the link successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
Reserved
Description
Reserved for Port Arbitration Table Offset (PATO)
Reserved
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is applicable
but is not set within the TLP Header will be rejected as an
Unsupported Request.
Reserved
Reserved for Port Arbitration Capability (PAC)
Datasheet, Volume 2

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