Peg_Cap-Pci Express-G Capabilities Register; Dcap-Device Capabilities Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.10.34 PEG_CAP—PCI Express-G Capabilities Register
This register indicates PCI Express device capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:14
13:9
8
7:4
3:0
2.10.35 DCAP—Device Capabilities Register
This register indicates PCI Express device capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:16
15
14:6
5
4:3
2:0
168
0/6/0/PCI
A2–A3h
0142h
RO, RW-O
16 bits
0h
Reset RST/
Attr
Value PWR
RO 0h
RO 00h Uncore
RW-O 1b Uncore
RO 4h Uncore
RO 2h Uncore
0/6/0/PCI
A4–A7h
00008000h
RO, RW-O
32 bits
0000000h
Reset RST/
Attr
Value PWR
RO 0h
RO 1b Uncore
RO 0h
RO 0b Uncore
RO 00b Uncore
RW-O 000b Uncore
Processor Configuration Registers
Description
Reserved
Interrupt Message Number (IMN)
Not Applicable or Implemented. Hardwired to 0.
Slot Implemented (SI)
0 = The PCI Express Link associated with this port is connected to
an integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to
a slot.
BIOS Requirement: This field must be initialized appropriately if
a slot connection is not implemented.
Device/Port Type (DPT)
Hardwired to 4h to indicate root port of PCI Express Root Complex.
PCI Express Capability Version (PCIECV)
Hardwired to 2h to indicate compliance to the PCI Express
Capabilities Register Expansion ECN.
Description
Reserved
Role Based Error Reporting (RBER)
Indicates that this device implements the functionality defined in
the Error Reporting ECN as required by the PCI Express 1.1
specification.
Reserved
Extended Tag Field Supported (ETFS)
Hardwired to indicate support for 5-bit Tags as a Requestor.
Phantom Functions Supported (PFS)
Not Applicable or Implemented. Hardwired to 0.
Max Payload Size
Default indicates 128B maximum supported payload for
Transaction Layer Packets (TLP.).
Datasheet, Volume 2