Pm_Capid1-Power Management Capabilities Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.25 PM_CAPID1—Power Management Capabilities Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:27
26
25
24:22
21
20
19
18:16
15:8
7:0
102
0/1/0–2/PCI
80–83h
C8039001h
RO, RO-V
32 bits
Reset RST/
Attr
Value PWR
RO 19h Uncore
RO 0b Uncore
RO 0b Uncore
RO 000b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 011b Uncore
RO-V 90h Uncore
RO 01h Uncore
Processor Configuration Registers
Description
PME Support (PMES)
This field indicates the power states in which this device may
indicate PME wake using PCI Express messaging. D0, D3hot &
D3cold. This device is not required to do anything to support D3hot
& D3cold; it simply must report that those states are supported.
Refer to the PCI Power Management 1.1 Specification for encoding
explanation and other power management details.
D2 Power State Support (D2PSS)
Hardwired to 0 to indicate that the D2 power management state is
NOT supported.
D1 Power State Support (D1PSS)
Hardwired to 0 to indicate that the D1 power management state is
NOT supported.
Auxiliary Current (AUXC)
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
Device Specific Initialization (DSI)
Hardwired to 0 to indicate that special initialization of this device is
NOT required before generic class device driver is to use it.
Auxiliary Power Source (APS)
Hardwired to 0.
PME Clock (PMECLK)
Hardwired to 0 to indicate this device does NOT support PME#
generation.
PCI PM CAP Version (PCIPMCV)
Version - A value of 011b indicates that this function complies with
revision 1.2 of the PCI Power Management Interface Specification.
Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list. If
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities
list is the Message Signaled Interrupts (MSI) capability at 90h. If
MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities
list is the PCI Express capability at A0h.
Capability ID (CID)
Value of 01h identifies this linked list item (capability structure) as
being for PCI Power Management registers.
Datasheet, Volume 2