Bga1023 Ballmap (Top View, Lower-Right Quadrant) - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

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Processor Pin and Signal Information
Figure 8-12. BGA1023 Ballmap (Top View, Lower-Right Quadrant)
VCC VSS VCC VSS
VSS VCC VSS VCC
VCC VCC VCC
VCC VCC VCC VCC
VCC VCC VCC VCC
VSS VCC VCC VCC
VSS VCC VCC VSS
VSS VCC VSS
VSS VCC VCC
VCC VCC VSS VCC VSS
31 30 29 28 27 26
Datasheet, Volume 1
VCCIO VSS
VSS VCCIO
VSS VCCSA
VCCSA VSS
VCCSA VSS
VSS VCCSA
VCCSA VSS VCCSA
VSS VCCSA VSS
PEG_RX[0 PEG_RX[1
RSVD VSS
]
PEG_RX#[
1]
PEG_RX#[ PEG_TX#[
VSS
0] 4]
PEG_TX#[ PEG_TX[4
0] ]
PEG_TX[0 PEG_TX#[
VSS
] 3]
PEG_TX[3
]
PEG_TX[2 PEG_TX#[ PEG_RX#[ PEG_RX[3
VSS
] 2] 3]
PEG_TX#[ PEG_RX[2 PEG_RX[4
1] ]
PEG_RX#[
2]
PEG_TX[1 PEG_RX#[
VSS
] 4]
25 24 23 22 21 20 19
VCCIO VSS VCCIO
VSS VCCIO
VSS VCCIO VSS
VCCIO VCCIO VSS
VSS VCCIO VCCIO VSS RSVD VSS
VCCSA VCCSA VCCSA
VCCSA RSVD VSS
VCCSA VSS VCCSA
VSS VCCSA VSS VSS RSVD
VSS VCCSA
VSS RSVD RSVD
VCCSA VSS
PEG_TX[6 PEG_TX#[ PEG_TX[1
] ] 6] 0]
PEG_TX#[
10]
PEG_TX#[
VSS VSS
11]
PEG_TX[7 PEG_TX[1
] 1]
PEG_TX#[ PEG_TX#[
VSS VSS
7] 8]
PEG_TX[8
]
PEG_RX#[ PEG_RX[5 PEG_RX#[
VSS VSS
] 5] ] 7]
PEG_TX#[ PEG_TX[9 PEG_RX[6
] 5] ] ]
PEG_TX[5 PEG_RX#[
] 6]
PEG_TX#[
VSS VSS
9]
18 17 16 15 14 13
FDI1_FSY FDI1_TX# FDI1_TX[
VSS
NC [3] 3]
FDI0_FSY FDI0_LSY FDI0_TX[ FDI0_TX#
VSS
NC NC 3]
FDI0_TX# FDI0_TX[ FDI1_TX[ FDI1_TX#
VSS
[1] 1] 0]
VCCSA_S FDI0_TX# FDI0_TX[
FDI_INT VSS
ENSE [0]
DMI_RX[ DMI_RX# DMI_RX[ DMI_RX#
VSS
3] [3] 1]
PEG_TX#[ DMI_TX# DMI_TX[
VSS
12] [1] 1]
PEG_TX[1 PEG_RX#[ PEG_RX[1
VSS VSS
2] 15]
PEG_RX#[ PEG_RX[1
VSS
13]
PEG_TX[1 PEG_RX#[
3] 10]
PEG_TX#[ PEG_RX[1 PEG_RX[1
13] 0]
PEG_RX[7 PEG_TX#[ PEG_TX[1
VSS
] 14] 4]
PEG_RX[8 PEG_RX[9 PEG_RX[1
] ] 1]
PEG_RX#[ PEG_RX#[
9]
PEG_RX#[ PEG_RX#[
VSS
8] 11]
12 11 10 9 8 7
eDP_ICO
VSS AD
MPO
eDP_TX#[ eDP_TX#[ eDP_TX[0
VSS AC
1] 0] ]
AB
eDP_TX[1 FDI1_TX[
VSS AA
[3] ] 2]
FDI1_TX#
VSS
[2]
FDI0_TX[ FDI0_TX#
[0] 2] [2]
FDI1_TX#
[1]
0]
FDI1_TX[ DMI_TX[
VSS
1] 3]
DMI_TX#
VSS
[3]
DMI_TX[ DMI_RX[ DMI_RX#
[1] 2] 2] [2]
DMI_TX# DMI_RX[
VSS
[2] 0]
DMI_RX#
VSS VSS
[0]
PEG_TX[1 DMI_TX[ DMI_TX#
5] 5] 0] [0]
PEG_TX#[
BCLK VSS
15]
VSS BCLK#
3]
PEG_IC
PEG_RCO PEG_ICO
VSS
OMPO
MPO MPI
4]
PEG_RX#[ VSS_NCT
VSS
14] F
DC_TEST DC_TEST
VSS VSS
_D3 _D1
PEG_RX[1 DC_TEST VSS_NCT
2] _C4 F
12]
VSS_NCT DC_TEST
F _A4
6 5 4 3 2 1
145
Y
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F
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A