Iqh_Reg-Invalidation Queue Head Register; Iqt_Reg-Invalidation Queue Tail Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.18.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:19
18:4
3:0
2.18.20 IQT_REG—Invalidation Queue Tail Register
This register indicates the invalidation tail head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:19
18:4
3:0
Datasheet, Volume 2
0/0/0/GFXVTBAR
80–87h
0000000000000000h
RO-V
64 bits
0000000000000h
Reset RST/
Attr
Value PWR
RO 0h
RO-V 0000h Uncore
RO 0h
0/0/0/GFXVTBAR
88–8Fh
0000000000000000h
RW-L
64 bits
0000000000000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 0000h Uncore
RO 0h
Description
Reserved
Queue Head (QH)
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be fetched next by hardware.
Hardware resets this field to 0 whenever the queued invalidation is
disabled (QIES field Clear in the Global Status register).
Reserved
Description
Reserved
Queue Tail (QT)
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be written next by software.
Reserved
239