Pm_Sref_Config-Self Refresh Configuration Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.16.4 PM_SREF_config—Self Refresh Configuration Register
This self refresh mode control register defines if and when DDR can go into SR.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:17
16
15:0
212
0/0/0/MCHBAR_MCMAIN
5060–5063h
000100FFh
RW-L
32 bits
0000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 1 Uncore
RW-L 00FFh Uncore
Processor Configuration Registers
Description
Reserved
Self‐refresh Enable
This control bit is an INTEL RESERVED bit. It is for test and
debug purposes only. This bit enables or disables self-refresh
mechanism.
Idle timer init value (Idle_timer)
This value is used when the "SREF_enable" field is set. It defines
the # of cycles, that there should not be any transaction to enter
self-refresh. It is programmable 1 to 64K–1. In DCLK=800 it
determines time of up to 82 us.
Datasheet, Volume 2