Rctl-Root Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
3
2
1
0
2.10.43 RCTL—Root Control Register
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:3
2
1:0
Datasheet, Volume 2
0/6/0/PCI
BA–BBh
0000h
RO, RO-V, RW1C
16 bits
00h
Reset RST/
Attr
Value PWR
RW1C 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
0/6/0/PCI
BC–BDh
0000h
RW, RO
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RW 0b Uncore
RO 0h
Description
Presence Detect Changed (PDC)
A pulse indication that the inband presence detect state has
changed.
This bit is set when the value reported in Presence Detect State is
changed.
Reserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL Sensor
state change is detected. If an MRL sensor is not implemented, this
bit must not be set.
Reserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is
implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware
capability, it is possible that a power fault can be detected at any
time, independent of the Power Controller Control setting or the
occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
Reserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the
attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
Description
Reserved
System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal error is
reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
Reserved
179