Sbusn1-Secondary Bus Number Register; Subusn1-Subordinate Bus Number Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.6.10 SBUSN1—Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.6.11 SUBUSN1—Subordinate Bus Number Register
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
Datasheet, Volume 2
0/1/0–2/PCI
19h
00h
RW
8 bits
Reset RST/
Attr
Value PWR
RW 00h Uncore
0/1/0–2/PCI
1Ah
00h
RW
8 bits
Reset RST/
Attr
Value PWR
RW 00h Uncore
Description
Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
Description
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the
processor root port bridge. When only a single PCI device resides
on the PCI Express-G segment, this register will contain the same
value as the SBUSN1 register.
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