Table Of Contents - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Contents
1 Introduction ............................................................................................................ 11
2 Processor Configuration Registers ........................................................................... 13
2.1 Register Terminology ......................................................................................... 13
2.2 PCI Devices and Functions on Processor ............................................................... 14
2.3 System Address Map ......................................................................................... 15
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
2.3.2.5
2.3.2.6
2.3.2.7
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.4
2.3.4.1
2.3.4.2
2.3.4.3
2.3.4.4
2.3.4.5
2.3.5
2.3.6
2.3.7
2.3.7.1
2.3.7.2
2.3.8
2.3.9
2.3.10
2.3.11
2.3.11.1 PCI Express* I/O Address Mapping.............................................. 36
2.3.12
2.3.13
2.3.13.1 DMI Interface Decode Rules ...................................................... 37
2.3.13.2 PCI Express* Interface Decode Rules........................................... 40
2.3.13.3 Legacy VGA and I/O Range Decode Rules..................................... 41
2.4 Processor Register Introduction ........................................................................... 45
2.4.1
2.5 PCI Device 0 Function 0 Configuration Space ........................................................ 46
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
Datasheet, Volume 2
Legacy Address Range ......................................................................... 18
DOS Range (0h-9_FFFFh) .......................................................... 18
Legacy Video Area (A_0000h-B_FFFFh) ....................................... 19
PAM (C_0000h-F_FFFFh) ........................................................... 20
Main Memory Address Range (1 MB - TOLUD) ......................................... 20
ISA Hole (15 MB-16 MB) ........................................................... 21
TSEG ...................................................................................... 21
Protected Memory Range (PMR) - (programmable) ....................... 21
DRAM Protected Range (DPR) ..................................................... 22
Pre-allocated Memory ............................................................... 22
GFX Stolen Spaces .................................................................... 23
ME UMA .................................................................................. 23
PCI Memory Address Range (TOLUD - 4 GB)........................................... 23
APIC Configuration Space (FEC0_0000h-FECF_FFFFh) ................... 25
HSEG (FEDA_0000h-FEDB_FFFFh) .............................................. 25
MSI Interrupt Memory Space (FEE0_0000h-FEEF_FFFFh) ............... 25
High BIOS Area ........................................................................ 25
Main Memory Address Space (4 GB to TOUUD)........................................ 26
Memory Re-claim Background .................................................... 27
Indirect Accesses to MCHBAR Registers........................................ 27
Memory Remapping .................................................................. 28
Hardware Remap Algorithm........................................................ 28
Programming Model .................................................................. 28
PCI Express* Configuration Address Space ............................................. 32
PCI Express* Graphics Attach (PEG) ...................................................... 33
Graphics Memory Address Ranges ......................................................... 34
IOBAR Mapped Access to Device 2 MMIO Space ............................ 34
Trusted Graphics Ranges ........................................................... 34
System Management Mode (SMM) ......................................................... 35
SMM and VGA Access through GTT TLB ................................................. 35
ME Stolen Memory Accesses ................................................................. 35
I/O Address Space .............................................................................. 36
MCTP and KVM Flows ........................................................................... 37
Decode Rules and Cross-Bridge Address Mapping .................................... 37
I/O Mapped Registers .......................................................................... 46
VID-Vendor Identification Register ....................................................... 48
DID-Device Identification Register........................................................ 48
PCICMD-PCI Command Register .......................................................... 49
PCISTS-PCI Status Register ................................................................ 50
RID-Revision Identification Register ..................................................... 52
CC-Class Code Register ...................................................................... 53
HDR-Header Type Register.................................................................. 53
SVID-Subsystem Vendor Identification Register ..................................... 54
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