Iqa_Reg-Invalidation Queue Address Register; Ics_Reg-Invalidation Completion Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.18.21 IQA_REG—Invalidation Queue Address Register
This register configures the base address and size of the invalidation queue. This
register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as
not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:39
38:12
11:3
2:0
2.18.22 ICS_REG—Invalidation Completion Status Register
This register reports the completion status of invalidation wait descriptor with the
Interrupt Flag (IF) Set.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:1
0
240
0/0/0/GFXVTBAR
90–97h
0000000000000000h
RW-L
64 bits
000000000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 0000000h Uncore
RO 0h
RW-L 0h Uncore
0/0/0/GFXVTBAR
9C–9Fh
00000000h
RW1CS
32 bits
00000000h
Reset RST/
Attr
Value PWR
RO 0h
Powerg
RW1CS 0b
ood
Processor Configuration Registers
Description
Reserved
Invalidation Queue Base Address (IQA)
This field points to the base of 4 KB aligned invalidation request
queue. Hardware ignores and does not implement bits 63:HAW,
where HAW is the host address width.
Reads of this field return the value that was last programmed to it.
Reserved
Queue Size (QS)
This field specifies the size of the invalidation request queue. A
value of X in this field indicates an invalidation request queue of
(2^X) 4KB pages. The number of entries in the invalidation queue
is 2^(X + 8).
Description
Reserved
Invalidation Wait Descriptor Complete (IWC)
This bit indicates completion of Invalidation Wait Descriptor with
Interrupt Flag (IF) field Set. Hardware implementations not
supporting queued invalidations implement this field as RsvdZ.
Datasheet, Volume 2