Lsts-Link Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.6.39 LSTS—Link Status Register
This register indicates PCI Express link status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15
14
13
12
11
Datasheet, Volume 2
0/1/0–2/PCI
B2–B3h
1001h
RO-V, RW1C, RO
16 bits
0h
Reset RST/
Attr
Value PWR
RW1C 0b Uncore
RW1C 0b Uncore
RO-V 0b Uncore
RO 1b Uncore
RO-V 0b Uncore
Description
Link Autonomous Bandwidth Status (LABWS)
This bit is set to 1 by hardware to indicate that hardware has
autonomously changed link speed or width, without the port
transitioning through DL_Down status, for reasons other than to
attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was
indicated as an autonomous change.
Link Bandwidth Management Status (LBWMS)
This bit is set to 1 by hardware to indicate that either of the
following has occurred without the port transitioning through
DL_Down status:
• A link retraining initiated by a write of 1b to the Retrain Link bit
has completed.
Note that this bit is set following any write of 1b to the Retrain
Link bit, including when the Link is in the process of retraining
for some other reason.
• Hardware has autonomously changed link speed or width to
attempt to correct unreliable link operation, either through an
TXTSSM time-out or a higher level process.
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the downstream component that
was not indicated as an autonomous change.
Data Link Layer Link Active (Optional) (DLLLA)
This bit indicates the status of the Data Link Control and
Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise.
This bit must be implemented if the corresponding Data Link Layer
Active Capability bit is implemented. Otherwise, this bit must be
hardwired to 0b.
Slot Clock Configuration (SCC)
0 = The device uses an independent clock irrespective of the
presence of a reference on the connector.
1 = The device uses the same physical reference clock that the
platform provides on the connector.
Link Training (TXTRN)
This bit indicates that the Physical Layer TXTSSM is in the
Configuration or Recovery state, or that 1b was written to the
Retrain Link bit but Link training has not yet begun. Hardware
clears this bit when the TXTSSM exits the Configuration/Recovery
state once Link training is complete.
113