Rctl-Root Control Register; Lctl2-Link Control 2 Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.43 RCTL—Root Control Register
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:3
2
1:0
2.6.44 LCTL2—Link Control 2 Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:13
12
120
0/1/0–2/PCI
BC–BDh
0000h
RO, RW
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RW 0b Uncore
RO 0h
0/1/0–2/PCI
D0–D1h
0002h
RWS, RWS-V
16 bits
0h
Reset RST/
Attr
Value PWR
RO 0h
Powerg
RWS 0b
ood
Processor Configuration Registers
Description
Reserved
System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal error is
reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
Reserved
Description
Reserved
Compliance De-emphasis (ComplianceDeemphasis)
This bit sets the de-emphasis level in Polling.Compliance state if
the entry occurred due to the Enter Compliance bit being 1b.
1 = -3.5 dB
0 = -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has
no effect. Components that support only 2.5 GT/s speed are
permitted to hardwire this bit to 0b.
For a Multi-Function device associated with an Upstream Port, the
bit in Function 0 is of type RWS, and only Function 0 controls the
component's Link behavior. In all other Functions of that device,
this bit is of type RsvdP..
This bit is intended for debug, compliance testing purposes.
System firmware and software is allowed to modify this bit only
during debug or compliance testing.
Datasheet, Volume 2