Pci Device 6 Extended Configuration; Pvccap1-Port Vc Capability Register 1; Pci Device 6 Extended Configuration Register Address Map - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.11

PCI Device 6 Extended Configuration

Table 2-13
the sections following the table.
Table 2-13. PCI Device 6 Extended Configuration Register Address Map
Address
Offset
0–FFh
100–103h
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–D37h
2.11.1 PVCCAP1—Port VC Capability Register 1
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:7
6:4
3:3
2:0
180
lists the registers arr anged by address offset. Register bit descriptions are in
Register
Symbol
RSVD Reserved
RSVD Reserved
PVCCAP1 Port VC Capability Register 1
PVCCAP2 Port VC Capability Register 2
PVCCTL Port VC Control
RSVD Reserved
VC0RCAP VC0 Resource Capability
VC0RCTL VC0 Resource Control
RSVD Reserved
VC0RSTS VC0 Resource Status
RSVD Reserved
0/6/0/MMR
104–107h
00000000h
RO
32 bits
0000000h
Reset RST/
Attr
Value PWR
RO 0h
RO 000b Uncore
RO 0h
RO 000b Uncore
Processor Configuration Registers
Register Name
Description
Reserved
Low Priority Extended VC Count (LPEVCC)
This field indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration. The value of 0 in this
field implies strict VC arbitration.
Reserved
Extended VC Count (EVCC)
This field indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.
Reset Value Access
0h RO
14010002h RO-V, RO
00000000h RO
00000000h RO
0000h RW, RO
0h RO
00000001h RO
800000FFh RO, RW
0h RO
0002h RO-V
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Datasheet, Volume 2