Peci Dc Characteristics; Example For Peci Host-Clients Connection; Peci Dc Electrical Limits - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Figure 7-1.

Example for PECI Host-clients Connection

7.10.2

PECI DC Characteristics

The PECI interface operates at a nominal voltage set by V
specifications shown in
V interface supply. V
CCIO
PECI devices will operate at the V
system. For specific nominal V
Table 7-15. PECI DC Electrical Limits
Symbol
Rup
V
in
V
hysteresis
V
n
V
p
C
bus
Cpad
Ileak000
Ileak025
Ileak050
Ileak075
Ileak100
Notes:
1. V
CCIO
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull up resistance measured at 0.75*V
104
Table 7-15
nominal levels will vary between processor families. All
CCIO
CCIO
Definition and Conditions
Internal pull up resistance
Input Voltage Range
Hysteresis
Negative-Edge Threshold Voltage
Positive-Edge Threshold Voltage
Bus Capacitance per Node
Pad Capacitance
leakage current @ 0V
leakage current @ 0.25*V
CCIO
leakage current @ 0.50*V
CCIO
leakage current @ 0.75*V
CCIO
leakage current @ V
CCIO
supplies the PECI interface. PECI behavior does not affect V
are used with devices normally operating from a
level determined by the processor installed in the
CCIO
levels, refer to Table
Min
15
-0.15
0.1 * V
CCIO
0.275 * V 0.500 * V
CCIO
0.550 * V 0.725 * V
CCIO
N/A
0.7
—
—
—
—
—
CCIO
CCIO
Electrical Specifications
The set of DC electrical
CCIO
7-6.
Max Units Notes
45 Ohm
V V
CCIO
N/A V
V
CCIO
V
CCIO
10 pF
1.8 pF
0.6 mA
0.4 mA
0.2 mA
0.13 mA
0.10 mA
min/max specifications.
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