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Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

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®
2nd Generation Intel
Core™
Processor Family Desktop
Datasheet – Volume 2
®
Supporting Intel
Core™ i7, i5 and i3 Desktop Processor Series
This is Volume 2 of 2
January 2011
Document Number: 324642-001

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  Summary of Contents for Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011

  • Page 1 ® 2nd Generation Intel Core™ Processor Family Desktop Datasheet – Volume 2 ® Supporting Intel Core™ i7, i5 and i3 Desktop Processor Series This is Volume 2 of 2 January 2011 Document Number: 324642-001...
  • Page 2: Datasheet, Volume

    Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.
  • Page 3: Table Of Contents

    Contents Introduction ......................11 Processor Configuration Registers ................13 Register Terminology ..................13 PCI Devices and Functions on Processor ............... 14 System Address Map ..................15 2.3.1 Legacy Address Range ................. 18 2.3.1.1 DOS Range (0h–9_FFFFh) ............18 2.3.1.2 Legacy Video Area (A_0000h–B_FFFFh) ........19 2.3.1.3 PAM (C_0000h–F_FFFFh) ............
  • Page 4 2.5.9 SID—Subsystem Identification Register ..........54 2.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register .......55 2.5.11 MCHBAR—Host Memory Mapped Register Range Base Register ....56 2.5.12 GGC—GMCH Graphics Control Register Register ........57 2.5.13 DEVEN—Device Enable Register.............59 2.5.14 PCIEXBAR—PCI Express Register Range Base Address Register....60 2.5.15 DMIBAR—Root Complex Register Range Base Address Register....62 2.5.16...
  • Page 5 2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register ..... 105 2.6.30 MC—Message Control Register ............106 2.6.31 MA—Message Address Register ............107 2.6.32 MD—Message Data Register ............... 107 2.6.33 PEG_CAPL—PCI Express-G Capability List Register ......... 107 2.6.34 PEG_CAP—PCI Express-G Capabilities Register ........108 2.6.35 DCAP—Device Capabilities Register............
  • Page 6 2.10.8 HDR6—Header Type Register .............. 149 2.10.9 PBUSN6—Primary Bus Number Register..........149 2.10.10 SBUSN6—Secondary Bus Number Register..........150 2.10.11 SUBUSN6—Subordinate Bus Number Register ........150 2.10.12 IOBASE6—I/O Base Address Register ........... 151 2.10.13 IOLIMIT6—I/O Limit Address Register ..........151 2.10.14 SSTS6—Secondary Status Register ............
  • Page 7 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register ......... 194 2.12.14 DMIESD—DMI Element Self Description Register ........195 2.12.15 DMILE1D—DMI Link Entry 1 Description Register........196 2.12.16 DMILE1A—DMI Link Entry 1 Address Register........196 2.12.17 DMILE2D—DMI Link Entry 2 Description Register........197 2.12.18 DMILE2A—DMI Link Entry 2 Address Register........
  • Page 8 2.18.25 IEUADDR_REG—Invalidation Event Upper Address Register ..... 242 2.18.26 IRTA_REG—Interrupt Remapping Table Address Register ......243 2.18.27 IVA_REG—Invalidate Address Register..........244 2.18.28 IOTLB_REG—IOTLB Invalidate Register..........245 2.18.29 FRCDL_REG—Fault Recording Low Register ........... 247 2.18.30 FRCDH_REG—Fault Recording High Register .......... 248 2.18.31 VTPOLICY—DMA Remap Engine Policy Control Register ......
  • Page 9 Figures System Address Range Example ................. 17 DOS Legacy Address Range ................18 Main Memory Address Range ................20 PCI Memory Address Range ................24 Case 1: Less than 4 GB of Physical Memory (no remap) ......... 29 Case 2: Greater than 4 GB of Physical Memory............30 Example: DMI Upstream VC0 Memory Map ............
  • Page 10: Revision History

    Revision History Revision Revision Description Number Date January Initial release 2011 § Datasheet, Volume 2...
  • Page 11: Introduction

    Introduction Introduction ® This is Volume 2 of the Datasheet for the 2nd Generation Intel Core™ processor family desktop. The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket.
  • Page 12 Introduction Datasheet, Volume 2...
  • Page 13: Processor Configuration Registers

    Processor Configuration Registers Processor Configuration Registers This chapter contains the following: • Register terminology • PCI Devices and Functions on Processor • System address map • Processor register introduction • Detailed register bit descriptions Register Terminology Table 2-1 shows the register-related terminology and register attributes that are used in this document.
  • Page 14: Pci Devices And Functions On Processor

    Processor Configuration Registers Table 2-2. Register Attribute Modifiers Attribute Applicable Description Modifier Attribute RO (w/ -V) Sticky: These bits are only re-initialized to their default value by a "Power Good Reset". RW1C Note: Does not apply to RO (constant) bits. RW1S Key: These bits control the ability to write other bits (identified with a 'Lock' modifier)
  • Page 15: System Address Map

    Processor Configuration Registers System Address Map The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has simpler mapping and is explained near the end of this section.
  • Page 16 3. In the case of overlapping ranges with memory, the memory decode will be given priority. This is a Intel TXT requirement. It is necessary to get Intel TXT protection checks, avoiding potential attacks. 4. There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges.
  • Page 17: System Address Range Example

    1 MB aligned 1 MB aligned Main memory OS visible Address > 4 GB Range 4 GB Flash, APIC OS invisible Intel TXT FEC0_0000 (20 MB) Reclaim 1 MB aligned TOLUD BASE for reclaim 1 MB aligned GFX Stolen Memory (0-256 MB) Add.
  • Page 18: Legacy Address Range

    Processor Configuration Registers 2.3.1 Legacy Address Range This area is divided into the following address regions: • 0–640 KB – DOS Area • 640–768 KB – Legacy Video Buffer Area • 768–896 KB in 16 KB sections (total of 8 sections) – Expansion Area •...
  • Page 19: Legacy Video Area (A_0000H-B_Ffffh)

    Processor Configuration Registers 2.3.1.2 Legacy Video Area (A_0000h–B_FFFFh) The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI Interface. The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits.
  • Page 20: Pam (C_0000H-F_Ffffh)

    TSEG, or optional ISA Hole, or optional IGD stolen VGA memory. Figure 2-3. Main Memory Address Range FFFF_FFFFh 4 GB Max FLASH APIC Intel TXT Contains: Dev 0, 1, 2, 6, 7 PCI Memory Range BARS & PCH/PCI ranges TOLUD...
  • Page 21: Isa Hole (15 Mb-16 Mb)

    Support for protected memory region is required for DMA-remapping hardware implementations on platforms supporting Intel TXT, and is optional for non-Intel TXT platforms. Since the protected memory region needs to be enabled before the MVMM is launched, hardware must support enabling of the protected memory region independently from enabling the DMA-remapping hardware.
  • Page 22: Dram Protected Range (Dpr)

    Processor Configuration Registers for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware implementations on platforms supporting Intel TXT are required to support protected high-memory region6, if the platform supports main memory above 4 GB. Once the protected low/high memory region registers are configured, bus master protection to these regions is enabled through the Protected Memory Enable register.
  • Page 23: Gfx Stolen Spaces

    Processor Configuration Registers 2.3.2.6 GFX Stolen Spaces 2.3.2.6.1 GTT Stolen Space (GSM) GSM is allocated to store the GFX translation table entries. GSM always exists regardless of VT-d as long as internal GFX is enabled. This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range.
  • Page 24: Pci Memory Address Range

    Processor Configuration Registers There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, MSI Interrupt Space, and High BIOS Address Range. The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges. Figure 2-4.
  • Page 25: Apic Configuration Space (Fec0_0000H-Fecf_Ffffh)

    Desktop systems. When disabled, any access within entire APIC Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI. 2.3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ® This decode range is not supported on the 2nd Generation Intel Core™ processor family desktop platform. 2.3.3.3 MSI Interrupt Memory Space (FEE0_0000h–FEEF_FFFFh) Any PCI Express or DMI device may issue a Memory Write to 0FEEx_xxxxh.
  • Page 26: Main Memory Address Space (4 Gb To Touud)

    Processor Configuration Registers 2.3.4 Main Memory Address Space (4 GB to TOUUD) The processor supports 39-bit addressing. The maximum main memory size supported is 32 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become relevant.
  • Page 27: Memory Re-Claim Background

    Processor Configuration Registers 2.3.4.1 Memory Re-claim Background The following are examples of Memory Mapped IO devices that are typically located below 4 GB: • High B I OS • TSEG • GFX s tolen • GTT s tolen • XAPIC •...
  • Page 28: Memory Remapping

    Processor Configuration Registers 2.3.4.3 Memory Remapping An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the REMAPBASE register. The top of the re-map window is defined by the value in the REMAPLIMIT register.
  • Page 29: Case 1: Less Than 4 Gb Of Physical Memory (No Remap)

    Processor Configuration Registers Case 1: Less than 4 GB of Physical Memory (no remap) Figure 2-5. Case 1: Less than 4 GB of Physical Memory (no remap) PHYSICAL MEMORY HOST/SYSTEM VIEW (DRAM CONTROLLER VIEW) 4 GB 1 MB aligned ME-UMA 1 MB aligned ME BASE TOUUD BASE...
  • Page 30: Case 2: Greater Than 4 Gb Of Physical Memory

    Example: 5 GB of Physical Memory, with 1 GB allocated to Memory Mapped IO: • Populated Physical Memory = 5 GB • Address Space allocated to memory mapped IO (including Flash, APIC, and Intel TXT) = 1 GB • Remapped Physical Memory = 1 GB •...
  • Page 31 Processor Configuration Registers The Remap window is inclusive of the Base and Limit addresses. In the decoder A[19:0] of the Remap Base Address are assumed to be 0s. Similarly, A[19:0] of the Remap Limit Address are assumed to be Fhs. Thus, the bottom of the defined memory range will be aligned to a megabyte boundary and the top of the defined range will be one less than a MB boundary.
  • Page 32: Pci Express* Configuration Address Space

    Processor Configuration Registers Implementation Notes • Remap applies to transactions from all interfaces. All upstream PEG/DMI transactions that are snooped get remapped. • Upstream PEG/DMI transactions that are not snooped (“Snoop not required” attribute set) get remapped. • Upstream reads and writes above TOUUD are treated as invalid cycles. •...
  • Page 33: Pci Express* Graphics Attach (Peg)

    Processor Configuration Registers 2.3.6 PCI Express* Graphics Attach (PEG) The processor can be programmed to direct memory accesses to a PCI Express interface. When addresses are within either of two ranges specified using registers in each PEG(s) configuration space. • The first range is controlled using the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers.
  • Page 34: Graphics Memory Address Ranges

    Processor Configuration Registers 2.3.7 Graphics Memory Address Ranges The MCH can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified using registers in the processor Device 2 configuration space. 1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated using the graphics translation table.
  • Page 35: System Management Mode (Smm)

    Processor Configuration Registers 2.3.8 System Management Mode (SMM) Unlike FSB platforms, the Core handles all SMM mode transaction routing. Also, the platform no longer supports HSEG. The processor will never allow I/O devices access to CSEG/TSEG/HSEG ranges. DMI Interface and PCI Express masters are not allowed to access the SMM space. Table 2-3.
  • Page 36: I/O Address Space

    Processor Configuration Registers 2.3.11 I/O Address Space The system agent generates either DMI Interface or PCI Express* bus cycles for all processor I/O accesses that it does not claim. Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to generate PCI configuration space access.
  • Page 37: Mctp And Kvm Flows

    Processor Configuration Registers The processor also forwards accesses to the Legacy VGA I/O ranges according to the settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE), unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit.
  • Page 38 Processor Configuration Registers DMI Interface Accesses to the processor that Cross Device Boundaries The processor does not support transactions that cross device boundaries. This should never occur because PCI Express transactions are not allowed to cross a 4 KB boundary. For reads, the processor will provide separate completion status for each naturally- aligned 64 byte block or, if chaining is enabled, each 128 byte block.
  • Page 39: Example: Dmi Upstream Vc0 Memory Map

    Processor Configuration Registers • VCm accesses — See the DMI2 specification for TC mapping to VCm. VCm access only map to ME stolen DRAM. These transactions carry the direct physical DRAM address (no redirection or remapping of any kind will occur). This is how the PCH Manageability engine accesses its dedicated DRAM stolen space.
  • Page 40: Pci Express* Interface Decode Rules

    Processor Configuration Registers 2.3.13.2 PCI Express* Interface Decode Rules All “SNOOP semantic” PCI Express transactions are kept coherent with processor caches. All “Snoop not required semantic” cycles must reference the direct DRAM address range. PCI-Express non-snoop initiated cycles are not snooped. If a “Snoop not required semantic”...
  • Page 41: Legacy Vga And I/O Range Decode Rules

    Processor Configuration Registers Figure 2-8. PEG Upstream VC0 Memory Map Upstream Initiated VC0 Cycle Memory Map TOM = total physical DRAM 64GB REMAPLIMIT TOUUD REMAPBASE FEE0_0000 – FEEF_FFFF( MSI) GMADR TOLUD TOLUD-(Gfx Stolen)-(Gfx GTT stolen) TSEG_BASE -(TSEG) TSEG_BASE - DPR A0000-BFFFF (VGA) mem writes ...
  • Page 42: Igd Frame Buffer Accesses

    Processor Configuration Registers Accesses to the VGA memory range are directed to IGD depend on the configuration. The configuration is specified by: • Internal Graphics Controller in Device 2 is enabled (DEVEN.D2EN bit 4) • Internal Graphics VGA in Device 0, function 0 is enabled through register GGC bit 1. •...
  • Page 43: Vga And Mda I/O Transaction Mapping

    Processor Configuration Registers For regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory range A0000h–BFFFFh is mapped either to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space, and the MDAPxx bits in the Legacy Access Control (LAC) register in Device 0 configuration space.
  • Page 44 Processor Configuration Registers MDA Present (MDAP): This bit works with the VGA Enable bit in th e BCTRL register of device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is not set.
  • Page 45: Processor Register Introduction

    (Reserved registers can be 8-, 16-, or 32 bits in size). Writes to Reserved registers have no effect on the processor. Registers that are marked as Intel Reserved must not be modified by system software. Writes to Intel Reserved registers may cause system failure.
  • Page 46: I/O Mapped Registers

    Processor Configuration Registers 2.4.1 I/O Mapped Registers The processor contains two registers that reside in the processor I/O address space— the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
  • Page 47 Processor Configuration Registers Table 2-7. PCI Device 0, Function 0 Register Address Map (Sheet 2 of 2) Address Register Register Name Reset Value Access Offset Symbol PAM1 Programmable Attribute Map 1 PAM2 Programmable Attribute Map 2 PAM3 Programmable Attribute Map 3 PAM4 Programmable Attribute Map 4 PAM5...
  • Page 48: Vid-Vendor Identification Register

    Reset RST/ Attr Description Value Vendor Identification Number (VID) 15:0 8086h Uncore PCI standard identification for Intel. 2.5.2 DID—Device Identification Register This register, combined with the Vendor Identification register, uniquely identifies any PCI device. B/D/F/Type: 0/0/0/PCI Address Offset: 2–3h Reset Value:...
  • Page 49: Pcicmd-Pci Command Register

    Processor Configuration Registers 2.5.3 PCICMD—PCI Command Register Since Device 0 does not physically reside on PCI_A, many of the bits are not implemented. B/D/F/Type: 0/0/0/PCI Address Offset: 4–5h Reset Value: 0006h Access: RO, RW Size: 16 bits BIOS Optimal Default Reset RST/ Attr...
  • Page 50: Pcists-Pci Status Register

    Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: 4–5h Reset Value: 0006h Access: RO, RW Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Bus Master Enable (BME) Uncore The processor is always enabled as a master on the backbone. This bit is hardwired to a 1.
  • Page 51 Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: 6–7h Reset Value: 0090h Access: RO, RW1C Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value DEVSEL Timing (DEVT) These bits are hardwired to "00". Writes to these bit positions have 10:9 Uncore no effect.
  • Page 52: Rid-Revision Identification Register

    This register contains the revision number of the processor. The SRID is a 8-bit hardwired value assigned by Intel, based on product stepping. The SRID is not a directly addressable PCI register. The SRID value is reflected through the RID register when appropriately addressed.
  • Page 53: Cc-Class Code Register

    Processor Configuration Registers 2.5.6 CC—Class Code Register This register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. B/D/F/Type: 0/0/0/PCI Address Offset: 9–Bh Reset Value: 060000h Access: Size: 24 bits Reset RST/ Attr Description Value Base Class Code (BCC)
  • Page 54: Svid-Subsystem Vendor Identification Register

    Processor Configuration Registers 2.5.8 SVID—Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem. B/D/F/Type: 0/0/0/PCI Address Offset: 2C–2Dh Reset Value: 0000h Access: RW-O Size: 16 bits Reset RST/ Attr Description Value Subsystem Vendor ID (SUBVID) This field should be programmed during boot-up to indicate the 15:0 RW-O...
  • Page 55: Pxpepbar-Pci Express Egress Port Base Address Register

    On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Device 0, offset 40h, bit 0]. All the bits in this register are locked in Intel TXT mode. B/D/F/Type:...
  • Page 56: Mchbar-Host Memory Mapped Register Range Base Register

    Host MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN [Device 0, offset 48h, bit 0]. All the bits in this register are locked in Intel TXT mode. The register space contains memory control, initialization, timing, and buffer strength registers;...
  • Page 57: Ggc-Gmch Graphics Control Register Register

    Processor Configuration Registers 2.5.12 GGC—GMCH Graphics Control Register Register All the bits in this register are Intel TXT lockable. B/D/F/Type: 0/0/0/PCI Address Offset: 50–51h Reset Value: 0028h Access: RW-KL, RW-L Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description...
  • Page 58 (bits 7:3 of this register) pre-allocates no memory. This bit MUST be set to 1 if Device 2 is disabled using a register (DEVEN[3] = 0). This register is locked by Intel TXT lock. GGC Lock (GGCLCK) RW-KL Uncore When set to 1b, this bit will lock all bits in this register.
  • Page 59: Deven-Device Enable Register

    This register allows for enabling/disabling of PCI devices and functions that are within the processor package. In the following table the bit definitions describe the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable. B/D/F/Type: 0/0/0/PCI Address Offset: 54–57h...
  • Page 60: Pciexbar-Pci Express Register Range Base Address Register

    512 GB. In general, system implementation and the number of PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the region. All the bits in this register are locked in Intel TXT mode. Datasheet, Volume 2...
  • Page 61 000h Uncore region defined by this register. This register is locked by Intel TXT. The address used to access the PCI Express configuration space for a specific device can be determined as follows: PCI Express Base Address + Bus Number * 1MB + Device...
  • Page 62: Dmibar-Root Complex Register Range Base Address Register

    This register ensures that a naturally aligned 4 KB space is allocated within the first 512 GB of addressable memory space. System Software uses this base address to program the DMI register set. All the Bits in this register are locked in Intel TXT mode. 11:1...
  • Page 63: Pam0-Programmable Attribute Map 0 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved Datasheet, Volume 2...
  • Page 64: Pam1-Programmable Attribute Map 1 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0C0000–0C3FFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
  • Page 65: Pam2-Programmable Attribute Map 2 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0C8000–0CBFFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
  • Page 66: Pam3-Programmable Attribute Map 3 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0D0000–0D3FFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
  • Page 67: Pam4-Programmable Attribute Map 4 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0D8000–0DBFFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh.
  • Page 68: Pam5-Programmable Attribute Map 5 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0E0000–0E3FFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
  • Page 69: Pam6-Programmable Attribute Map 6 Register

    10 = Write Only. All writes are sent to DRAM, all reads are serviced by DMI. 11 = Normal DRAM Operation. All reads and writes are serviced by DRAM. This register is locked by Intel TXT. Reserved 0E8000–0EBFFF Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0E8000h to 0EBFFFh.
  • Page 70: Lac-Legacy Access Control Register

    Uncore 0 = No memory hole. 1 = Memory hole from 15 MB to 16 MB. This bit is Intel TXT lockable. Reserved PEG60 MDA Present (MDAP60) This bit works with the VGA Enable bits in the BCTRL register of...
  • Page 71 Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: Reset Value: Access: Size: 8 bits BIOS Optimal Default Reset RST/ Attr Description Value PEG12 MDA Present (MDAP12) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
  • Page 72 Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: Reset Value: Access: Size: 8 bits BIOS Optimal Default Reset RST/ Attr Description Value PEG11 MDA Present (MDAP11) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
  • Page 73 Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: Reset Value: Access: Size: 8 bits BIOS Optimal Default Reset RST/ Attr Description Value PEG10 MDA Present (MDAP10) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
  • Page 74: Remapbase-Remap Base Address Register

    FFFFh Uncore 1 MB boundary. When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. These bits are Intel TXT lockable. 19:1 Reserved Lock (LOCK) RW-KL Uncore This bit will lock all writeable settings in this register, including itself.
  • Page 75: Tom-Top Of Memory Register

    (holes may exist in main memory address map due to addresses allocated for memory mapped IO). These bits correspond to address bits 38:20 (1 MB granularity). Bits 19:0 are assumed to be 0. All the bits in this register are locked in Intel TXT mode. Reserved 19:1...
  • Page 76: Touud-Top Of Upper Usable Dram Register

    The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB. All the bits in this register are locked in Intel TXT mode. 19:1 Reserved...
  • Page 77: Bdsm-Base Data Of Stolen Memory Register

    Processor Configuration Registers 2.5.28 BDSM—Base Data of Stolen Memory Register This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0, offset BCh, bits 31:20).
  • Page 78: G Memory Base Register

    • The system memory requirements are: 4 GB (max addressable space) – 1 GB (pci space) = 0_C000_0000hSince 0_C000_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD should be programmed to C00h. These bits are Intel TXT lockable. Datasheet, Volume 2...
  • Page 79: Skpd-Scratchpad Data Register

    Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by TSEG size to determine base of TSEG. All the Bits in this register are locked in Intel TXT mode. This register must be 1MB aligned when reclaim is enabled. 19:1...
  • Page 80: Capid0_A-Capabilities A Register

    Processor Configuration Registers 2.5.33 CAPID0_A—Capabilities A Register This register control of bits in this register are only required for customer visible SKU differentiation. B/D/F/Type: 0/0/0/PCI Address Offset: E4–E7h Default Value: 00000000h Access: RO-FW, RO-KFW Size: 32 bits BIOS Optimal Default: 000000h Reset RST/...
  • Page 81 Processor Configuration Registers B/D/F/Type: 0/0/0/PCI Address Offset: E4–E7h Default Value: 00000000h Access: RO-FW, RO-KFW Size: 32 bits BIOS Optimal Default: 000000h Reset RST/ Attr Description Value RO-FW Reserved Reserved DDR3 Maximum Frequency Capability (DMFC) This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h).
  • Page 82: Pci Device 1 Function 0-2 Configuration Space

    Processor Configuration Registers PCI Device 1 Function 0–2 Configuration Space Table 2-8 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-8. PCI Device 1, Function 0–2 Configuration Register Address Map (Sheet 1 of 2) Address Register Reset...
  • Page 83 Processor Configuration Registers Table 2-8. PCI Device 1, Function 0–2 Configuration Register Address Map (Sheet 2 of 2) Address Register Reset Register Name Access Offset Symbol Value 92–93h Message Control 0000h RO, RW 94–97h Message Address 00000000h RW, RO 98–99h Message Data 0000h 9A–9Fh...
  • Page 84: Vid1-Vendor Identification Register

    Reset RST/ Attr Description Value Vendor Identification (VID) 15:0 8086h Uncore PCI standard identification for Intel. 2.6.2 DID1—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: 0/1/0–2/PCI Address Offset: 2–3h Reset Value: See Section 2.2...
  • Page 85: Pcicmd1-Pci Command Register

    Processor Configuration Registers 2.6.3 PCICMD1—PCI Command Register B/D/F/Type: 0/1/0–2/PCI Address Offset: 4–5h Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:11 Reserved INTA Assertion Disable (INTAAD) 0 = This device is permitted to generate INTA interrupt messages 1 = This device is prevented from generating interrupt messages.
  • Page 86 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: 4–5h Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Bus Master Enable (BME) This bit controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction.
  • Page 87: Pcists1-Pci Status Register

    Processor Configuration Registers 2.6.4 PCISTS1—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the Root port. B/D/F/Type: 0/1/0–2/PCI Address Offset: 6–7h Reset Value: 0010h Access: RW1C, RO, RO-V Size: 16 bits BIOS Optimal Default...
  • Page 88 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: 6–7h Reset Value: 0010h Access: RW1C, RO, RO-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Master Data Parity Error (PMDPE) This bit is Set by a Requester (Primary Side for Type 1 Configuration Space header Function) if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs:...
  • Page 89: Rid1-Revision Identification Register

    This is an 8-bit value that indicates the revision identification RO-FW Uncore ® number for the root port. Refer to the 2nd Generation Intel Core™ Processor Family Desktop Specification Update for the value of the RID register. Revision Identification Number (RID) This is an 8-bit value that indicates the revision identification ®...
  • Page 90: Cl1-Cache Line Size Register

    Processor Configuration Registers 2.6.7 CL1—Cache Line Size Register B/D/F/Type: 0/1/0–2/PCI Address Offset: Reset Value: Access: Size: 8 bits Reset RST/ Attr Description Value Cache Line Size (CLS) Implemented by PCI Express devices as a read-write field for Uncore legacy compatibility purposes but has no impact on any PCI Express device functionality.
  • Page 91: Sbusn1-Secondary Bus Number Register

    Processor Configuration Registers 2.6.10 SBUSN1—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: 0/1/0–2/PCI Address Offset:...
  • Page 92: Iobase1-I/O Base Address Register

    Processor Configuration Registers 2.6.12 IOBASE1—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE  address  IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0.
  • Page 93: Ssts1-Secondary Status Register

    Processor Configuration Registers 2.6.14 SSTS1—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor. B/D/F/Type: 0/1/0–2/PCI Address Offset: 1E–1Fh Reset Value:...
  • Page 94: Mbase1-Memory Base Address Register

    Processor Configuration Registers 2.6.15 MBASE1—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address.
  • Page 95: Mlimit1-Memory Limit Address Register

    Processor Configuration Registers 2.6.16 MLIMIT1—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address.
  • Page 96: Pmbase1-Prefetchable Memory Base Address Register

    Processor Configuration Registers 2.6.17 PMBASE1—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
  • Page 97: Pmlimit1-Prefetchable Memory Limit Address Register

    Processor Configuration Registers 2.6.18 PMLIMIT1—Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
  • Page 98: Pmbaseu1-Prefetchable Memory Base Address Upper Register

    Processor Configuration Registers 2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ...
  • Page 99: Capptr1-Capabilities Pointer Register

    Processor Configuration Registers 2.6.21 CAPPTR1—Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. B/D/F/Type: 0/1/0–2/PCI Address Offset: Reset Value: Access: Size: 8 bits Reset RST/ Attr Description Value...
  • Page 100: Intrpin1-Interrupt Pin Register

    Processor Configuration Registers 2.6.23 INTRPIN1—Interrupt Pin Register This register specifies which interrupt pin this device uses. B/D/F/Type: 0/1/0–2/PCI Address Offset: Reset Value: Access: RW-O, RO Size: 8 bits Reset RST/ Attr Description Value Uncore Interrupt Pin High (INTPINH) Interrupt Pin (INTPIN) As a multifunction device, the PCI Express device may specify any INTx (x=A, B, C, D) as its interrupt pin.
  • Page 101 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: 3E–3Fh Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Secondary Bus Reset (SRESET) Setting this bit triggers a hot reset on the corresponding PCI Uncore Express Port.
  • Page 102: Pm_Capid1-Power Management Capabilities Register

    Processor Configuration Registers 2.6.25 PM_CAPID1—Power Management Capabilities Register B/D/F/Type: 0/1/0–2/PCI Address Offset: 80–83h Reset Value: C8039001h Access: RO, RO-V Size: 32 bits Reset RST/ Attr Description Value PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging.
  • Page 103: Pm_Cs1-Power Management Control/Status Register

    Processor Configuration Registers 2.6.26 PM_CS1—Power Management Control/Status Register B/D/F/Type: 0/1/0–2/PCI Address Offset: 84–87h Reset Value: 00000008h Access: RO, RW Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value 31:16 Reserved PME Status (PMESTS) Uncore This bit indicates that this device does not support PME# generation from D3cold.
  • Page 104: Ss_Capid-Subsystem Id And Vendor Id Capabilities Register

    Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: 84–87h Reset Value: 00000008h Access: RO, RW Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Power State (PS) This field indicates the current power state of this device and can be used to set the device into a new power state.
  • Page 105: Ss-Subsystem Id And Subsystem Vendor Id Register

    Processor Configuration Registers 2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and a hardware reset. B/D/F/Type: 0/1/0–2/PCI Address Offset: 8C–8Fh Reset Value: 00008086h...
  • Page 106: Mc-Message Control Register

    Processor Configuration Registers 2.6.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
  • Page 107: Ma-Message Address Register

    Processor Configuration Registers 2.6.31 MA—Message Address Register B/D/F/Type: 0/1/0–2/PCI Address Offset: 94–97h Reset Value: 00000000h Access: RW, RO Size: 32 bits Reset RST/ Attr Description Value Message Address (MA) 00000000 Used by system software to assign an MSI address to the device. 31:2 Uncore The device handles an MSI by writing the padded contents of the...
  • Page 108: Peg_Cap-Pci Express-G Capabilities Register

    Processor Configuration Registers 2.6.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: 0/1/0–2/PCI Address Offset: A2–A3h Reset Value: 0142h Access: RO, RW-O Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:14 Reserved Interrupt Message Number (IMN) 13:9 Uncore Not Applicable or Implemented.
  • Page 109: Dctl-Device Control Register

    Processor Configuration Registers 2.6.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
  • Page 110: Dsts-Device Status Register

    Processor Configuration Registers 2.6.37 DSTS—Device Status Register Reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type: 0/1/0–2/PCI Address Offset: AA–ABh Reset Value: 0000h...
  • Page 111: Lctl-Link Control Register

    Processor Configuration Registers 2.6.38 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: 0/1/0–2/PCI Address Offset: B0–B1h Reset Value: 0000h Access: RW, RO, RW-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:12 Reserved Link Autonomous Bandwidth Interrupt Enable (LABIE) When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been...
  • Page 112 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: B0–B1h Reset Value: 0000h Access: RW, RO, RW-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Common Clock Configuration (CCC) 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.
  • Page 113: Lsts-Link Status Register

    Processor Configuration Registers 2.6.39 LSTS—Link Status Register This register indicates PCI Express link status. B/D/F/Type: 0/1/0–2/PCI Address Offset: B2–B3h Reset Value: 1001h Access: RO-V, RW1C, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Link Autonomous Bandwidth Status (LABWS) This bit is set to 1 by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than to...
  • Page 114: Slotcap-Slot Capabilities Register

    Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: B2–B3h Reset Value: 1001h Access: RO-V, RW1C, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 10:10 Reserved Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
  • Page 115 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: B4–B7h Reset Value: 00040000h Access: RW-O, RO Size: 32 bits Reset RST/ Attr Description Value Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 16:15 RW-O...
  • Page 116: Slotctl-Slot Control Register

    Processor Configuration Registers 2.6.41 SLOTCTL—Slot Control Register PCI Express Slot related registers allow for the support of Hot Plug. B/D/F/Type: 0/1/0–2/PCI Address Offset: B8–B9h Reset Value: 0000h Access: Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:13 Reserved Reserved for Data Link Layer State Changed Enable (DLLSCE)
  • Page 117 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: B8–B9h Reset Value: 0000h Access: Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
  • Page 118: Slotsts-Slot Status Register

    Processor Configuration Registers 2.6.42 SLOTSTS—Slot Status Register PCI Express Slot related registers. B/D/F/Type: 0/1/0–2/PCI Address Offset: BA–BBh Reset Value: 0000h Access: RO, RO-V, RW1C Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:9 Reserved Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
  • Page 119 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: BA–BBh Reset Value: 0000h Access: RO, RO-V, RW1C Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has RW1C Uncore changed...
  • Page 120: Rctl-Root Control Register

    Processor Configuration Registers 2.6.43 RCTL—Root Control Register This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link.
  • Page 121 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: D0–D1h Reset Value: 0002h Access: RWS, RWS-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Compliance SOS (compsos) When set to 1b, the TXTSSM is required to send SKP Ordered Sets periodically in between the (modified) compliance patterns.
  • Page 122 Processor Configuration Registers B/D/F/Type: 0/1/0–2/PCI Address Offset: D0–D1h Reset Value: 0002h Access: RWS, RWS-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Target Link Speed (TLS) For Downstream ports, this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences.
  • Page 123: Pci Device 1 Function 0-2 Extended Configuration

    Processor Configuration Registers PCI Device 1 Function 0–2 Extended Configuration Table 2-9 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-9. PCI Device 1 Function 0–2 Extended Configuration Register Address Map Address Register Reset...
  • Page 124: Pvccap2-Port Vc Capability Register 2

    Processor Configuration Registers 2.7.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: 0/1/0–2/MMR Address Offset: 108–10Bh Reset Value: 00000000h Access: Size: 32 bits BIOS Optimal Default 0000h Reset RST/ Attr Description...
  • Page 125: Vc0Rcap-Vc0 Resource Capability Register

    Processor Configuration Registers 2.7.4 VC0RCAP—VC0 Resource Capability Register B/D/F/Type: 0/1/0–2/MMR Address Offset: 110–113h Reset Value: 00000001h Access: Size: 32 bits BIOS Optimal Default Reset RST/ Attr Description Value 31:24 Uncore Reserved for Port Arbitration Table Offset (PATO) 23:23 Reserved 22:16 Uncore Reserved for Maximum Time Slots (MTS) Reject Snoop Transactions (RSNPT)
  • Page 126: Vc0Rctl-Vc0 Resource Control Register

    Processor Configuration Registers 2.7.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: 0/1/0–2/MMR Address Offset: 114–117h Reset Value: 800000FFh Access: RO, RW Size: 32 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value...
  • Page 127: Vc0Rsts-Vc0 Resource Status Register

    Processor Configuration Registers 2.7.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: 0/1/0–2/MMR Address Offset: 11A–11Bh Reset Value: 0002h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:2 Reserved VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete.
  • Page 128: Pci Device 2 Configuration Space

    Processor Configuration Registers PCI Device 2 Configuration Space Table 2-10 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-10. PCI Device 2 Configuration Register Address Map Address Register Reset Register Name Access Offset...
  • Page 129: Vid2-Vendor Identification Register

    Value Vendor Identification Number (VID) 15:0 8086h Uncore PCI standard identification for Intel. 2.8.2 DID2—Device Identification Register This register, combined with the Vendor Identification register, uniquely identifies any PCI device. This is a 16-bit value assigned to processor graphics device.
  • Page 130: Pcicmd2-Pci Command Register

    Processor Configuration Registers 2.8.3 PCICMD2—PCI Command Register This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. B/D/F/Type: 0/2/0/PCI Address Offset: 4–5h Reset Value:...
  • Page 131: Pcists2-Pci Status Register

    Processor Configuration Registers 2.8.4 PCISTS2—PCI Status Register PCISTS is a 16-bit statu s register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. B/D/F/Type: 0/2/0/PCI Address Offset:...
  • Page 132: Rid2-Revision Identification Register

    Reset RST/ Attr Description Value Revision Identification Number MSB (RID_MSB) ® Four MSB of RID. Refer to the 2nd Generation Intel Core™ RO-FW Uncore Processor Family Desktop Specification Update for the value of the RID register. Revision Identification Number (RID) ®...
  • Page 133: Cls-Cache Line Size Register

    Processor Configuration Registers 2.8.7 CLS—Cache Line Size Register The IGD does not support this register as a PCI slave. B/D/F/Type: 0/2/0/PCI Address Offset: Reset Value: Access: Size: 8 bits Reset RST/ Attr Description Value Cache Line Size (CLS) This field is hardwired to 0s. The IGD as a PCI compliant master Uncore does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size.
  • Page 134: Gttmmadr-Graphics Translation Table, Memory Mapped Range Address Register

    Processor Configuration Registers 2.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with 2MB of that used by MMIO and 2 MB used by GTT. GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR.
  • Page 135: Gmadr-Graphics Memory Range Address Register

    Processor Configuration Registers 2.8.11 GMADR—Graphics Memory Range Address Register GMADR is the PCI aperture used by software to access tiled GFX surfaces in a linear fashion. B/D/F/Type: 0/2/0/PCI Address Offset: 18–1Fh Reset Value: 000000000000000Ch Access: RO, RW-L, RW Size: 64 bits Reset RST/ Attr...
  • Page 136: Iobar-I/O Base Address Register

    Processor Configuration Registers 2.8.12 IOBAR—I/O Base Address Register This register provides the Base offset of the I/O registers within Device 2. Bits 15:6 are programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded.
  • Page 137: Sid2-Subsystem Identification Register

    Processor Configuration Registers 2.8.14 SID2—Subsystem Identification Register This register is used to uniquely identify the subsystem where the PCI device resides. B/D/F/Type: 0/2/0/PCI Address Offset: 2E–2Fh Reset Value: 0000h Access: RW-O Size: 16 bits Reset RST/ Attr Description Value Subsystem Identification (SUBID) This value is used to identify a particular subsystem.
  • Page 138: Mingnt-Minimum Grant Register

    Processor Configuration Registers 2.8.17 MINGNT—Minimum Grant Register The Integrated Graphics Device has no requirement for the settings of Latency Timers. B/D/F/Type: 0/2/0/PCI Address Offset: Reset Value: Access: Size: 8 bits Reset RST/ Attr Description Value Minimum Grant Value (MGV) Uncore The IGD does not burst as a PCI compliant master.
  • Page 139: Msac-Multi Size Aperture Control Register

    System BIOS needs to save this value on boot so that it can reset it correctly during S3 resume. Note: This register is Intel TXT locked and becomes read only when the trusted environment is launched. B/D/F/Type:...
  • Page 140: Device 2 Io

    Processor Configuration Registers Device 2 IO Table 2-11. Device 2 IO Register Address Map Address Register Reset Register Name Access Offset Symbol Value 0–3h Index MMIO Address Register 00000000h 4–7h Data MMIO Data Register 00000000h 2.9.1 INDEX—MMIO Address Register A 32-bit I/O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed.
  • Page 141: Pci Device 6

    Processor Configuration Registers 2.10 PCI Device 6 Table 2-12 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-12. PCI Device 6 Register Address Map (Sheet 1 of 2) Address Register Register Name Reset Value Access...
  • Page 142 Processor Configuration Registers Table 2-12. PCI Device 6 Register Address Map (Sheet 2 of 2) Address Register Register Name Reset Value Access Offset Symbol 92–93h Message Control 0000h RO, RW 94–97h Message Address 00000000h RW, RO 98–99h Message Data 0000h 9A–9Fh RSVD Reserved...
  • Page 143: Vid6-Vendor Identification Register

    Reset RST/ Attr Description Value Vendor Identification (VID) 15:0 8086h Uncore PCI standard identification for Intel. 2.10.2 DID6—Device Identification Register This register, combined with the Vendor Identification register, uniquely identifies any PCI device. B/D/F/Type: 0/6/0/PCI Address Offset: 2–3h Reset Value:...
  • Page 144: Pcicmd6-Pci Command Register

    Processor Configuration Registers 2.10.3 PCICMD6—PCI Command Register B/D/F/Type: 0/6/0/PCI Address Offset: 4–5h Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:11 Reserved INTA Assertion Disable (INTAAD) 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages.
  • Page 145 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: 4–5h Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Bus Master Enable (BME) Controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction.
  • Page 146: Pcists6-Pci Status Register

    Processor Configuration Registers 2.10.4 PCISTS6—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the Root port. B/D/F/Type: 0/6/0/PCI Address Offset: 6–7h Reset Value: 0010h Access: RW1C, RO, RO-V Size: 16 bits BIOS Optimal Default...
  • Page 147 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: 6–7h Reset Value: 0010h Access: RW1C, RO, RO-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Master Data Parity Error (PMDPE) This bit is set by a Requester (Primary Side for Type 1 Configuration Space header Function) if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs:...
  • Page 148: Rid6-Revision Identification Register

    This is an 8-bit value that indicates the revision identification RO-FW Uncore ® number for the root port. Refer to the 2nd Generation Intel Core™ Processor Family Desktop Specification Update for the value of the RID register. Revision Identification Number (RID) This is an 8-bit value that indicates the revision identification ®...
  • Page 149: Cl6-Cache Line Size Register

    Processor Configuration Registers 2.10.7 CL6—Cache Line Size Register B/D/F/Type: 0/6/0/PCI Address Offset: Reset Value: Access: Size: 8 bits Reset RST/ Attr Description Value Cache Line Size (CLS) Implemented by PCI Express devices as a read-write field for Uncore legacy compatibility purposes but has no impact on any PCI Express device functionality.
  • Page 150: Sbusn6-Secondary Bus Number Register

    Processor Configuration Registers 2.10.10 SBUSN6—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: 0/6/0/PCI Address Offset:...
  • Page 151: Iobase6-I/O Base Address Register

    Processor Configuration Registers 2.10.12 IOBASE6—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE  address  IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0.
  • Page 152: Ssts6-Secondary Status Register

    Processor Configuration Registers 2.10.14 SSTS6—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor. B/D/F/Type: 0/6/0/PCI Address Offset: 1E–1Fh Reset Value:...
  • Page 153: Mbase6-Memory Base Address Register

    Processor Configuration Registers 2.10.15 MBASE6—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address.
  • Page 154: Mlimit6-Memory Limit Address Register

    Processor Configuration Registers 2.10.16 MLIMIT6—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address.
  • Page 155: Pmbase6-Prefetchable Memory Base Address Register

    Processor Configuration Registers 2.10.17 PMBASE6—Prefetchable Memory Base Address Register This register, in conjunction with the corresponding Upper Base Address register, controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
  • Page 156: Pmlimit6-Prefetchable Memory Limit Address Register

    Processor Configuration Registers 2.10.18 PMLIMIT6—Prefetchable Memory Limit Address Register This register, in conjunction with the corresponding Upper Limit Address register, controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
  • Page 157: Pmbaseu6-Prefetchable Memory Base Address Upper Register

    Processor Configuration Registers 2.10.19 PMBASEU6—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ...
  • Page 158: Pmlimitu6-Prefetchable Memory Limit Address Upper Register

    Processor Configuration Registers 2.10.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ...
  • Page 159: Intrline6-Interrupt Line Register

    Processor Configuration Registers 2.10.22 INTRLINE6—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: 0/6/0/PCI Address Offset: Reset Value: Access:...
  • Page 160: Bctrl6-Bridge Control Register

    Processor Configuration Registers 2.10.24 BCTRL6—Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (that is, PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" Host- PCI Express bridge embedded within the processor (such as, VGA compatible address ranges mapping).
  • Page 161 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: 3E–3Fh Reset Value: 0000h Access: RO, RW Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value ISA Enable (ISAEN) Needed to exclude legacy resource decode to route ISA resources to legacy decode path. Modifies the response by the root port to an I/O access issued by the processor that target ISA I/O addresses.
  • Page 162: Pm_Capid6-Power Management Capabilities Register

    Processor Configuration Registers 2.10.25 PM_CAPID6—Power Management Capabilities Register B/D/F/Type: 0/6/0/PCI Address Offset: 80–83h Reset Value: C8039001h Access: RO, RO-V Size: 32 bits Reset RST/ Attr Description Value PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging.
  • Page 163: Pm_Cs6-Power Management Control/Status Register

    Processor Configuration Registers 2.10.26 PM_CS6—Power Management Control/Status Register B/D/F/Type: 0/6/0/PCI Address Offset: 84–87h Reset Value: 00000008h Access: RO, RW Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value 31:16 Reserved PME Status (PMESTS) Uncore This bit indicates that this device does not support PME# generation from D3cold.
  • Page 164: Ss_Capid-Subsystem Id And Vendor Id Capabilities Register

    Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: 84–87h Reset Value: 00000008h Access: RO, RW Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Power State (PS) This field indicates the current power state of this device and can be used to set the device into a new power state.
  • Page 165: Ss-Subsystem Id And Subsystem Vendor Id Register

    Processor Configuration Registers 2.10.28 SS—Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and a hardware reset. B/D/F/Type: 0/6/0/PCI Address Offset: 8C–8Fh Reset Value: 00008086h...
  • Page 166: Mc-Message Control Register

    Processor Configuration Registers 2.10.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing If the device writes the same message multiple times, only one of those messages is assured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
  • Page 167: Ma-Message Address Register

    Processor Configuration Registers 2.10.31 MA—Message Address Register B/D/F/Type: 0/6/0/PCI Address Offset: 94–97h Reset Value: 00000000h Access: RW, RO Size: 32 bits Reset RST/ Attr Description Value Message Address (MA) This field is used by system software to assign an MSI address to 31:2 00000000h Uncore...
  • Page 168: Peg_Cap-Pci Express-G Capabilities Register

    Processor Configuration Registers 2.10.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: 0/6/0/PCI Address Offset: A2–A3h Reset Value: 0142h Access: RO, RW-O Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:14 Reserved Interrupt Message Number (IMN) 13:9 Uncore Not Applicable or Implemented.
  • Page 169: Dctl-Device Control Register

    Processor Configuration Registers 2.10.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
  • Page 170: Dsts-Device Status Register

    Processor Configuration Registers 2.10.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type: 0/6/0/PCI Address Offset: AA–ABh...
  • Page 171: Lctl-Link Control Register

    Processor Configuration Registers 2.10.38 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: 0/6/0/PCI Address Offset: B0–B1h Reset Value: 0000h Access: RO, RW, RW-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:12 Reserved Link Autonomous Bandwidth Interrupt Enable (LABIE) When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been...
  • Page 172 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: B0–B1h Reset Value: 0000h Access: RO, RW, RW-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Common Clock Configuration (CCC) 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.
  • Page 173: Lsts-Link Status Register

    Processor Configuration Registers 2.10.39 LSTS—Link Status Register This register indicates PCI Express link status. B/D/F/Type: 0/6/0/PCI Address Offset: B2–B3h Reset Value: 1001h Access: RW1C, RO-V, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Link Autonomous Bandwidth Status (LABWS) This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than to...
  • Page 174: Slotcap-Slot Capabilities Register

    Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: B2–B3h Reset Value: 1001h Access: RW1C, RO-V, RO Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 10:10 Reserved Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
  • Page 175 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: B4–B7h Reset Value: 00040000h Access: RW-O, RO Size: 32 bits Reset RST/ Attr Description Value Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 16:15 RW-O...
  • Page 176: Slotctl-Slot Control Register

    Processor Configuration Registers 2.10.41 SLOTCTL—Slot Control Register PCI Express Slot related registers allow for the support of Hot Plug. B/D/F/Type: 0/6/0/PCI Address Offset: B8–B9h Reset Value: 0000h Access: Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:13 Reserved Reserved for Data Link Layer State Changed Enable (DLLSCE)
  • Page 177 Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: B8–B9h Reset Value: 0000h Access: Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
  • Page 178: Slotsts-Slot Status Register

    Processor Configuration Registers 2.10.42 SLOTSTS—Slot Status Register This is for PCI Express Slot related registers. B/D/F/Type: 0/6/0/PCI Address Offset: BA–BBh Reset Value: 0000h Access: RO, RO-V, RW1C Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:9 Reserved Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
  • Page 179: Rctl-Root Control Register

    Processor Configuration Registers B/D/F/Type: 0/6/0/PCI Address Offset: BA–BBh Reset Value: 0000h Access: RO, RO-V, RW1C Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has RW1C Uncore changed.
  • Page 180: Pci Device 6 Extended Configuration

    Processor Configuration Registers 2.11 PCI Device 6 Extended Configuration Table 2-13 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-13. PCI Device 6 Extended Configuration Register Address Map Address Register Register Name Reset Value...
  • Page 181: Pvccap2-Port Vc Capability Register 2

    Processor Configuration Registers 2.11.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: 0/6/0/MMR Address Offset: 108–10Bh Reset Value: 00000000h Access: Size: 32 bits BIOS Optimal Default 0000h Reset RST/ Attr Description...
  • Page 182: Vc0Rcap-Vc0 Resource Capability Register

    Processor Configuration Registers 2.11.4 VC0RCAP—VC0 Resource Capability Register B/D/F/Type: 0/6/0/MMR Address Offset: 110–113h Reset Value: 00000001h Access: Size: 32 bits BIOS Optimal Default Reset RST/ Attr Description Value 31:24 Uncore Reserved for Port Arbitration Table Offset (PATO) 23:23 Reserved 22:16 Uncore Reserved for Maximum Time Slots (MTS) Reject Snoop Transactions (RSNPT)
  • Page 183: Vc0Rctl-Vc0 Resource Control Register

    Processor Configuration Registers 2.11.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: 0/6/0/MMR Address Offset: 114–117h Reset Value: 800000FFh Access: RO, RW Size: 32 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value...
  • Page 184: Vc0Rsts-Vc0 Resource Status Register

    Processor Configuration Registers 2.11.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: 0/6/0/MMR Address Offset: 11A–11Bh Reset Value: 0002h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:2 Reserved VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete.
  • Page 185: Dmibar

    Processor Configuration Registers 2.12 DMIBAR Table 2-14 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-14. DMIBAR Register Address Map (Sheet 1 of 2) Address Register Reset Register Name Access Offset Symbol Value...
  • Page 186: Dmivcech-Dmi Virtual Channel Enhanced Capability Register

    Processor Configuration Registers Table 2-14. DMIBAR Register Address Map (Sheet 2 of 2) Address Register Reset Register Name Access Offset Symbol Value 88–89h LCTL Link Control 0000h RW, RW-V 8A–8Bh LSTS DMI Link Status 0001h RO-V 8C–97h RSVD Reserved Link Control 2 RWS, 98–99h LCTL2...
  • Page 187: Dmipvccap1-Dmi Port Vc Capability Register 1

    Processor Configuration Registers 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 4–7h Reset Value: 00000000h Access: RO, RW-O Size: 32 bits BIOS Optimal Default 0000000h Reset RST/...
  • Page 188: Dmipvcctl-Dmi Port Vc Control Register

    Processor Configuration Registers 2.12.4 DMIPVCCTL—DMI Port VC Control Register B/D/F/Type: 0/0/0/DMIBAR Address Offset: C–Dh Reset Value: 0000h Access: RW, RO Size: 16 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value 15:4 Reserved VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field.
  • Page 189: Dmivc0Rctl-Dmi Vc0 Resource Control Register

    Processor Configuration Registers 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 14–17h Reset Value: 8000007Fh Access: RO, RW Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description...
  • Page 190: Dmivc0Rsts-Dmi Vc0 Resource Status Register

    Processor Configuration Registers 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 1A–1Bh Reset Value: 0002h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:2 Reserved Virtual Channel 0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete.
  • Page 191: Dmivc1Rctl-Dmi Vc1 Resource Control Register

    Processor Configuration Registers 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 20–23h Reset Value: 01000000h Access: RO, RW Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description...
  • Page 192: Dmivc1Rsts-Dmi Vc1 Resource Status Register

    Processor Configuration Registers 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 26–27h Reset Value: 0002h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:2 Reserved Virtual Channel 1 Negotiation Pending (VC1NP) 0 = The VC negotiation is complete.
  • Page 193: Dmivcprctl-Dmi Vcp Resource Control Register

    Processor Configuration Registers 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel (VCp). B/D/F/Type: 0/0/0/DMIBAR Address Offset: 2C–2Fh Reset Value: 02000000h Access: RO, RW Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description...
  • Page 194: Dmivcprsts-Dmi Vcp Resource Status Register

    Processor Configuration Registers 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 32–33h Reset Value: 0002h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:2 Reserved Virtual Channel private Negotiation Pending (VCPNP) 0 = The VC negotiation is complete.
  • Page 195: Dmiesd-Dmi Element Self Description Register

    Processor Configuration Registers 2.12.14 DMIESD—DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 44–47h Reset Value: 01000202h Access: RO, RW-O Size: 32 bits BIOS Optimal Default Reset RST/ Attr...
  • Page 196: Dmile1D-Dmi Link Entry 1 Description Register

    Processor Configuration Registers 2.12.15 DMILE1D—DMI Link Entry 1 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 50–53h Reset Value: 00000000h Access: RW-O, RO Size: 32 bits BIOS Optimal Default...
  • Page 197: Dmile2D-Dmi Link Entry 2 Description Register

    Processor Configuration Registers 2.12.17 DMILE2D—DMI Link Entry 2 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 60–63h Reset Value: 00000000h Access: RO, RW-O Size: 32 bits BIOS Optimal Default...
  • Page 198: Lcap-Link Capabilities Register

    Processor Configuration Registers 2.12.19 LCAP—Link Capabilities Register This register indicates DMI specific capabilities. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 84–87h Reset Value: 00012C41h Access: RW-O, RO, RW-OV Size: 32 bits BIOS Optimal Default 00002h Reset RST/ Attr Description Value 31:18 Reserved L1 Exit Latency (L1SELAT) This field indicates the length of time this Port requires to complete the transition from L1 to L0.
  • Page 199: Lctl-Link Control Register

    Processor Configuration Registers 2.12.20 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 88–89h Reset Value: 0000h Access: RW, RW-V Size: 16 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value 15:10 Reserved Hardware Autonomous Width Disable (HAWD) When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link...
  • Page 200: Lsts-Dmi Link Status Register

    Processor Configuration Registers 2.12.21 LSTS—DMI Link Status Register This register indicates DMI status. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 8A–8Bh Reset Value: 0001h Access: RO-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:12 Reserved Link Training (TXTRN) When set, this bit indicates that the Physical Layer TXTSSM is in the Configuration or Recovery state, or that 1b was written to the RO-V Uncore...
  • Page 201: Lctl2-Link Control 2 Register

    Processor Configuration Registers 2.12.22 LCTL2—Link Control 2 Register B/D/F/Type: 0/0/0/DMIBAR Address Offset: 98–99h Reset Value: 0002h Access: RWS, RWS-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value 15:13 Reserved Compliance De-emphasis (ComplianceDeemphasis) This bit sets the de-emphasis level in Polling. Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
  • Page 202 Processor Configuration Registers B/D/F/Type: 0/0/0/DMIBAR Address Offset: 98–99h Reset Value: 0002h Access: RWS, RWS-V Size: 16 bits BIOS Optimal Default Reset RST/ Attr Description Value Powerg Selectable De-emphasis (selectabledeemphasis) When the Link is operating at 5 GT/s speed, this bit selects the level of de-emphasis.
  • Page 203: Lsts2-Link Status 2 Register

    Processor Configuration Registers 2.12.23 LSTS2—Link Status 2 Register B/D/F/Type: 0/0/0/DMIBAR Address Offset: 9A–9Bh Reset Value: 0000h Access: RO-V Size: 16 bits BIOS Optimal Default 0000h Reset RST/ Attr Description Value 15:1 Reserved Current De-emphasis Level (CURDELVL) When the Link is operating at 5 GT/s speed, this reflects the level of de-emphasis.
  • Page 204: Mchbar Registers In Memory Controller - Channel 0

    Processor Configuration Registers 2.13 MCHBAR Registers in Memory Controller – Channel 0 Table 2-15 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-15. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map Address Reset Register Symbol...
  • Page 205: Tc_Rfp_C0-Refresh Parameters Register

    Processor Configuration Registers 2.13.2 TC_RFP_C0—Refresh Parameters Register B/D/F/Type: 0/0/0/MCHBAR MC0 Address Offset: 4294-4297h Default Value: 0000980Fh Access: RW-L Size: 32 bits BIOS Optimal Default: 0000h Reset RST/ Attr Description Value 31:18 Reserved Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable. 00b = Double refresh rate when DRAM is WARM/HOT.
  • Page 206: Mchbar Registers In Memory Controller - Channel 1

    Processor Configuration Registers 2.14 MCHBAR Registers in Memory Controller – Channel 1 Table 2-16 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-16. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map Address Reset Register Symbol...
  • Page 207: Tc_Rfp_C1-Refresh Parameters Register

    Processor Configuration Registers 2.14.2 TC_RFP_C1—Refresh Parameters Register B/D/F/Type: 0/0/0/MCHBAR MC1 Address Offset: 4694–4697h Default Value: 0000980Fh Access: RW-L Size: 32 bits BIOS Optimal Default: 0000h Reset RST/ Attr Description Value 31:18 Reserved Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable. 00b = Double refresh rate when DRAM is WARM/HOT.
  • Page 208: Mchbar Registers In Memory Controller - Integrated Memory Peripheral Hub (Imph)

    Processor Configuration Registers 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH) Table 2-17 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-17. MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub Address Reset Register Symbol...
  • Page 209: Mchbar Registers In Memory Controller - Common

    Processor Configuration Registers 2.16 MCHBAR Registers in Memory Controller – Common Table 2-18 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-18. MCHBAR Registers in Memory Controller – Common Register Address Map Address Register Reset...
  • Page 210: Mad_Dimm_Ch0-Address Decode Channel 0 Register

    Processor Configuration Registers 2.16.2 MAD_DIMM_ch0—Address decode channel 0 Register This register defines channel characteristics—number of DIMMs, number of ranks, size, interleave options B/D/F/Type: 0/0/0/MCHBAR_MCMAIN Address Offset: 5004–5007h Reset Value: 00600000h Access: RW-L Size: 32 bits BIOS Optimal Default Reset RST/ Attr Description Value...
  • Page 211: Mad_Dimm_Ch1 - Address Decode Channel 1 Register

    Processor Configuration Registers 2.16.3 MAD_DIMM_ch1 - Address Decode Channel 1 Register This register defines channel characteristics—number of DIMMs, number of ranks, size, interleave options B/D/F/Type: 0/0/0/MCHBAR_MCMAIN Address Offset: 5008–500Bh Reset Value: 00600000h Access: RW-L Size: 32 bits BIOS Optimal Default Reset RST/ Attr...
  • Page 212: Pm_Sref_Config-Self Refresh Configuration Register

    Attr Description Value 31:17 Reserved Self‐refresh Enable This control bit is an INTEL RESERVED bit. It is for test and RW-L Uncore debug purposes only. This bit enables or disables self-refresh mechanism. Idle timer init value (Idle_timer) This value is used when the “SREF_enable” field is set. It defines...
  • Page 213: Memory Controller Mmio Registers Broadcast Group

    Processor Configuration Registers 2.17 Memory Controller MMIO Registers Broadcast Group Table 2-19 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-19. Memory Controller MMIO Registers Broadcast Group Register Address Map Address Reset Register Symbol...
  • Page 214: Pm_Cmd_Pwr-Power Management Command Power Register

    Processor Configuration Registers 2.17.2 PM_CMD_PWR—Power Management Command Power Register This register defines the power contribution of each command - ACT+PRE, CAS-read and CAS write. Assumption is that the ACT is always followed by a PRE (although not immediately), and REF commands are issued in a fixed rate and there is no need to count them.
  • Page 215: Integrated Graphics Vtd Remapping Engine Registers

    Processor Configuration Registers 2.18 Integrated Graphics VTd Remapping Engine Registers Table 2-20 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-20. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 1 of Address Register Register Name...
  • Page 216: Ver_Reg-Version Register

    Processor Configuration Registers Table 2-20. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 2 of Address Register Register Name Reset Value Access Offset Symbol A8–ABhh IEADDR_REG Invalidation Event Address Register 00000000h RW-L AC–AFh IEUADDR_REG Invalidation Event Upper Address Register 00000000h RW-L B0–B7h...
  • Page 217: Cap_Reg-Capability Register

    Processor Configuration Registers 2.18.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 8–Fh Reset Value: 00C0000020E60262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value 63:56 Reserved DMA Read Draining (DRD): Uncore 0 = Hardware does not support draining of DMA read requests.
  • Page 218 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 8–Fh Reset Value: 00C0000020E60262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value Isochrony (ISOCH) 0 = Remapping hardware unit has no critical isochronous requesters in its scope. 1 = Remapping hardware unit has one or more critical isochronous Uncore requesters in its scope.
  • Page 219 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 8–Fh Reset Value: 00C0000020E60262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value Caching Mode (CM) 0 = Not-present and erroneous entries are not cached in any of the remapping caches. Invalidations are not required for modifications to individual not present or invalid entries.
  • Page 220: Ecap_Reg-Extended Capability Register

    1 = Hardware supports IOTXTB caching hints through the ALH and EH fields in context entries. Extended Interrupt Mode (EIM) 0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode). RO-V Uncore 1 = On Intel 64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode).
  • Page 221 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 10–17h Reset Value: 0000000000F0101Ah Access: RO, RO-V Size: 64 bits BIOS Optimal Default 00000000000h Reset RST/ Attr Description Value Device IOTLB Support (DI) 0 = Hardware does not support device-IOTLBs. Uncore 1 = Hardware supports Device-IOTLBs. Implementations reporting this field as set must also support Queued Invalidation (QI).
  • Page 222: Gcmd_Reg-Global Command Register

    Processor Configuration Registers 2.18.4 GCMD_REG—Global Command Register This register controls remapping hardware. If multiple control fields in this register need to be modified, software must serialize the modifications through multiple writes to this register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 18–1Bh Reset Value: 00000000h Access: RO, WO...
  • Page 223 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 18–1Bh Reset Value: 00000000h Access: RO, WO Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Set Fault Log (SFL) This field is valid only for implementations supporting advanced fault logging. Software sets this field to request hardware to set/update the fault-log pointer used by hardware.
  • Page 224 This field is valid only for Intel 64 implementations supporting interrupt-remapping. Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms. The value in this field is effective only when interrupt-remapping is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
  • Page 225: Gsts_Reg-Global Status Register

    Processor Configuration Registers 2.18.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 1C–1Fh Reset Value: 00000000h Access: RO, RO-V Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
  • Page 226: Rtaddr_Reg-Root-Entry Table Address Register

    Interrupt Remapping Table Address register. Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt-remapping. The value reported in this field is applicable only when interrupt- RO-V Uncore remapping is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
  • Page 227: Ccmd_Reg-Context Command Register

    Processor Configuration Registers 2.18.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 28–2Fh Reset Value: 0800000000000000h...
  • Page 228 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 28–2Fh Reset Value: 0800000000000000h Access: RW, RW-V, RO-V Size: 64 bits BIOS Optimal Default 000000000h Reset RST/ Attr Description Value Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field).
  • Page 229: Fsts_Reg-Fault Status Register

    Processor Configuration Registers 2.18.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 34–37h Reset Value: 00000000h Access: RO, ROS-V, RW1CS Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description Value 31:16 Reserved Fault Record Index (FRI) This field is valid only when the PPF field is set.
  • Page 230 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 34–37h Reset Value: 00000000h Access: RO, ROS-V, RW1CS Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description Value Advanced Fault Overflow (AFO) Hardware sets this bit to indicate advanced fault log overflow condition.
  • Page 231: Fectl_Reg-Fault Event Control Register

    Processor Configuration Registers 2.18.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 38–3Bh Reset Value: 80000000h Access: RW, RO-V Size: 32 bits BIOS Optimal Default 00000000h Reset RST/ Attr Description Value Interrupt Mask (IM) 0 = No masking of interrupt.
  • Page 232: Fedata_Reg-Fault Event Data Register

    Processor Configuration Registers 2.18.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 3C–3Fh Reset Value: 00000000h Access: Size: 32 bits Reset RST/ Attr Description Value Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit 31:16 0000h Uncore...
  • Page 233: Aflog_Reg-Advanced Fault Log Register

    Processor Configuration Registers 2.18.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register). B/D/F/Type: 0/0/0/GFXVTBAR Address Offset:...
  • Page 234: Pmen_Reg-Protected Memory Enable Register

    Processor Configuration Registers 2.18.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register).
  • Page 235: Plmbase_Reg-Protected Low-Memory Base Register

    Processor Configuration Registers 2.18.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
  • Page 236: Plmlimit_Reg-Protected Low-Memory Limit Register

    Processor Configuration Registers 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
  • Page 237: Phmbase_Reg-Protected High-Memory Base Register

    Processor Configuration Registers 2.18.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
  • Page 238: Phmlimit_Reg-Protected High-Memory Limit Register

    Processor Configuration Registers 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
  • Page 239: Iqh_Reg-Invalidation Queue Head Register

    Processor Configuration Registers 2.18.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 80–87h Reset Value: 0000000000000000h Access:...
  • Page 240: Iqa_Reg-Invalidation Queue Address Register

    Processor Configuration Registers 2.18.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset:...
  • Page 241: Iectl_Reg-Invalidation Event Control Register

    Processor Configuration Registers 2.18.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: A0–A3h Reset Value: 80000000h...
  • Page 242: Iedata_Reg-Invalidation Event Data Register

    Processor Configuration Registers 2.18.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: A4–A7h Reset Value: 00000000h...
  • Page 243: Irta_Reg-Interrupt Remapping Table Address Register

    Reads of this field returns value that was last programmed to it. Extended Interrupt Mode Enable (EIME) This field is used by hardware on Intel 64 platforms as follows: 0 = xAPIC mode is active. Hardware interprets only low 8-bits of Destination-ID field in the IRTEs.
  • Page 244: Iva_Reg-Invalidate Address Register

    Processor Configuration Registers 2.18.27 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write only register. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 100–107h Reset Value: 0000000000000000h Access: Size:...
  • Page 245: Iotlb_Reg-Iotlb Invalidate Register

    Processor Configuration Registers 2.18.28 IOTLB_REG—IOTLB Invalidate Register This register invalidates the IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT bit set causes the hardware to perform the IOTLB invalidation. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 108–10Fh Reset Value: 0200000000000000h Access: RW-V, RW, RO-V...
  • Page 246 Processor Configuration Registers B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: 108–10Fh Reset Value: 0200000000000000h Access: RW-V, RW, RO-V Size: 64 bits BIOS Optimal Default 0000000000000h Reset RST/ Attr Description Value IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field).
  • Page 247: Frcdl_Reg-Fault Recording Low Register

    Processor Configuration Registers 2.18.29 FRCDL_REG—Fault Recording Low Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
  • Page 248: Frcdh_Reg-Fault Recording High Register

    Processor Configuration Registers 2.18.30 FRCDH_REG—Fault Recording High Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
  • Page 249: Vtpolicy-Dma Remap Engine Policy Control Register

    Processor Configuration Registers 2.18.31 VTPOLICY—DMA Remap Engine Policy Control Register This register contains all the policy bits related to the DMA remap engine. B/D/F/Type: 0/0/0/GFXVTBAR Address Offset: FF0–FF3h Reset Value: 00000000h Access: RO, RO-KFW, RW-KL, RW-L Size: 32 bits BIOS Optimal Default 0000h Reset RST/...
  • Page 250: Pcu Mchbar Registers

    Processor Configuration Registers 2.19 PCU MCHBAR Registers Table 2-21 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-21. PCU MCHBAR Register Address Map Register Reset Register Symbol Register Name Access Start Value...
  • Page 251: Mem_Trml_Estimation_Config-Memory Thermal Estimation Configuration Register

    Processor Configuration Registers 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register This register contains configuration regarding VTS temperature estimation calculations that are done by PCODE. For the BW estimation mode, the following formula is used: VTS temperature estimation = T(n) + VTS_Offset where T(n) = (1 –...
  • Page 252: Mem_Trml_Thresholds_Config-Memory Thermal Thresholds Configuration Register

    Processor Configuration Registers 2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register This register describes the thresholds for the memory thermal management in the MC. • The warm threshold defines when self-refresh is at double rate. Throttling can also be applied at this threshold based on the configuration in the MC. •...
  • Page 253: Mem_Trml_Status_Report-Memory Thermal Status Report Register

    Processor Configuration Registers 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register This register reports the thermal status of DRAM. B/D/F/Type: 0/0/0/MCHBAR PCU Address Offset: 58A0–58A3h Reset Value: 00000000h Access: RO-V Size: 32 bits BIOS Optimal Default Reset RST/ Attr Description Value 31:25 Reserved Double Self refresh (DSR) RO-V...
  • Page 254: Mem_Trml_Temperature_Report-Memory Thermal Temperature Report Register

    Processor Configuration Registers 2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register This register is used to report the estimated thermal status of the memory. The Channel VTS estimated maximum temperature field is used to report the estimated maximum temperature of all ranks. B/D/F/Type: 0/0/0/MCHBAR PCU Address Offset:...
  • Page 255: Gt_Perf_Status-Gt Performance Status Register

    Processor Configuration Registers 2.19.6 GT_PERF_STATUS—GT Performance Status Register P-state encoding for the Secondary Power Plane's current PLL frequency and the current VID. B/D/F/Type: 0/0/0/MCHBAR PCU Address Offset: 5948-594Bh Default Value: 00000000h Access: RO-V; Size: 32 bits BIOS Optimal Default 0000h Reset Attr RST/PWR...
  • Page 256: Sskpd-Sticky Scratchpad Data Register

    Processor Configuration Registers 2.19.8 SSKPD—Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. B/D/F/Type: 0/0/0/MCHBAR PCU Address Offset: 5D10–5D17h Reset Value: 0000000000000000h Access: Size: 64 bits Reset RST/...
  • Page 257 Processor Configuration Registers B/D/F/Type: 0/0/0/MCHBAR PCU Address Offset: 5D10–5D17h Reset Value: 0000000000000000h Access: Size: 64 bits Reset RST/ Attr Description Value Self Refresh Latency Time (WM1) Number of microseconds to access memory if memory is in Self Refresh (0.5 us granularity). 00h = 0 us 01h = 0.5 us 02h = 1 us...
  • Page 258: Pxpepbar

    Processor Configuration Registers 2.20 PXPEPBAR Table 2-22 lists the registers arr anged by address offset. Register bit descriptions are in the sections following the table. Table 2-22. PXPEPBAR Register Address Map Address Register Register Name Reset Value Access Offset Symbol 0–13h RSVD Reserved...
  • Page 259: Default Peg/Dmi Vtd Remapping Engine Registers

    Processor Configuration Registers 2.21 Default PEG/DMI VTd Remapping Engine Registers Table 2-23 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-23. Default PEG/DMI VTd Remapping Engine Register Address Map (Sheet 1 of 2) Address Register Register Name...
  • Page 260: Ver_Reg-Version Register

    Processor Configuration Registers Table 2-23. Default PEG/DMI VTd Remapping Engine Register Address Map (Sheet 2 of 2) Address Register Register Name Reset Value Access Offset Symbol A8–ABh IEADDR_REG Invalidation Event Address Register 00000000h RW-L AC–AFh IEUADDR_REG Invalidation Event Upper Address Register 00000000h RW-L B0–B7h...
  • Page 261: Cap_Reg-Capability Register

    Processor Configuration Registers 2.21.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 8–Fh Reset Value: 00C9008020660262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value 63:56 Reserved DMA Read Draining (DRD) Uncore 0 = Hardware does Not support draining of DMA read requests.
  • Page 262 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 8–Fh Reset Value: 00C9008020660262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value Isochrony (ISOCH) 0 = Remapping hardware unit has no critical isochronous requesters in its scope. 1 = Remapping hardware unit has one or more critical Uncore isochronous requesters in its scope.
  • Page 263 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 8–Fh Reset Value: 00C9008020660262h Access: Size: 64 bits BIOS Optimal Default 000h Reset RST/ Attr Description Value Caching Mode (CM) 0 = Not-present and erroneous entries are Not cached in any of the remapping caches. Invalidations are not required for modifications to individual not present or invalid entries.
  • Page 264: Ecap_Reg-Extended Capability Register

    1 = Hardware supports IOTXTB caching hints through the ALH and EH fields in context-entries. Extended Interrupt Mode (EIM) 0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode). RO-V Uncore 1 = On Intel 64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode).
  • Page 265 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 10–17h Reset Value: 0000000000F010DAh Access: RO-V, RO Size: 64 bits BIOS Optimal Default 00000000000h Reset RST/ Attr Description Value Device IOTLB Support (DI) 0 = Hardware does not support device-IOTLBs. Uncore 1 = Hardware supports Device-IOTLBs. Implementations reporting this field as set must also support Queued Invalidation (QI).
  • Page 266: Gcmd_Reg-Global Command Register

    Processor Configuration Registers 2.21.4 GCMD_REG—Global Command Register This register controls remapping hardware. If multiple control fields in this register need to be modified, software must serialize the modifications through multiple writes to this register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 18–1Bh Reset Value: 00000000h Access: WO, RO...
  • Page 267 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 18–1Bh Reset Value: 00000000h Access: WO, RO Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Set Fault Log (SFL) This field is valid only for implementations supporting advanced fault logging. Software sets this field to request hardware to set/update the fault-log pointer used by hardware.
  • Page 268 This field is valid only for Intel 64 implementations supporting interrupt-remapping. Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms. The value in this field is effective only when interrupt-remapping is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
  • Page 269: Gsts_Reg-Global Status Register

    Processor Configuration Registers 2.21.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 1C–1Fh Reset Value: 00000000h Access: RO, RO-V Size: 32 bits BIOS Optimal Default 000000h Reset RST/ Attr Description Value Translation Enable Status (TES) This bit indicates the status of DMA-remapping hardware.
  • Page 270: Rtaddr_Reg-Root-Entry Table Address Register

    Interrupt Remapping Table Address register. Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt-remapping. The value reported in this field is applicable only when interrupt- RO-V Uncore remapping is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
  • Page 271: Ccmd_Reg-Context Command Register

    Processor Configuration Registers 2.21.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 28–2Fh Reset Value: 0000000000000000h...
  • Page 272 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 28–2Fh Reset Value: 0000000000000000h Access: RW-V, RW, RO-V Size: 64 bits BIOS Optimal Default 000000000h Reset RST/ Attr Description Value Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field).
  • Page 273: Fsts_Reg-Fault Status Register

    Processor Configuration Registers 2.21.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 34–37h Reset Value: 00000000h Access: RW1CS, ROS-V, RO Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description Value 31:16 Reserved Fault Record Index (FRI) This field is valid only when the PPF field is Set.
  • Page 274 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 34–37h Reset Value: 00000000h Access: RW1CS, ROS-V, RO Size: 32 bits BIOS Optimal Default 00000h Reset RST/ Attr Description Value Advanced Fault Overflow (AFO) Hardware sets this field to indicate advanced fault log overflow condition.
  • Page 275: Fectl_Reg-Fault Event Control Register

    Processor Configuration Registers 2.21.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 38-3Bh Reset Value: 80000000h Access: RW, RO-V Size: 32 bits BIOS Optimal Default 00000000h Reset RST/ Attr Description Value Interrupt Mask (IM) 0 = No masking of interrupt.
  • Page 276: Fedata_Reg-Fault Event Data Register

    Processor Configuration Registers 2.21.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 3C–3Fh Reset Value: 00000000h Access: Size: 32 bits Reset RST/ Attr Description Value Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit 31:16 0000h Uncore...
  • Page 277: Aflog_Reg-Advanced Fault Log Register

    Processor Configuration Registers 2.21.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register). B/D/F/Type: 0/0/0/VC0PREMAP Address Offset:...
  • Page 278: Pmen_Reg-Protected Memory Enable Register

    Processor Configuration Registers 2.21.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register).
  • Page 279: Plmbase_Reg-Protected Low-Memory Base Register

    Processor Configuration Registers 2.21.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
  • Page 280: Plmlimit_Reg-Protected Low-Memory Limit Register

    Processor Configuration Registers 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
  • Page 281: Phmbase_Reg-Protected High-Memory Base Register

    Processor Configuration Registers 2.21.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
  • Page 282: Phmlimit_Reg-Protected High-Memory Limit Register

    Processor Configuration Registers 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
  • Page 283: Iqh_Reg-Invalidation Queue Head Register

    Processor Configuration Registers 2.21.19 IQH_REG—Invalidation Queue Head Register Register indicating the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 80–87h Reset Value: 0000000000000000h Access: RO-V...
  • Page 284: Iqa_Reg-Invalidation Queue Address Register

    Processor Configuration Registers 2.21.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset:...
  • Page 285: Iectl_Reg-Invalidation Event Control Register

    Processor Configuration Registers 2.21.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: A0–A3h Reset Value: 80000000h...
  • Page 286: Iedata_Reg-Invalidation Event Data Register

    Processor Configuration Registers 2.21.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: A4–A7h Reset Value: 00000000h...
  • Page 287: Ieuaddr_Reg-Invalidation Event Upper Address Register

    Reads of this field returns value that was last programmed to it. Extended Interrupt Mode Enable (EIME) This field is used by hardware on Intel 64 platforms as follows: 0 = xAPIC mode is active. Hardware interprets only low 8-bits of Destination-ID field in the IRTEs.
  • Page 288: Iva_Reg-Invalidate Address Register

    Processor Configuration Registers 2.21.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write only register. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 100–107h Reset Value: 0000000000000000h Access: Size:...
  • Page 289: Iotlb_Reg-Iotlb Invalidate Register

    Processor Configuration Registers 2.21.29 IOTLB_REG—IOTLB Invalidate Register Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field Set causes the hardware to perform the IOTLB invalidation. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 108–10Fh Reset Value: 0000000000000000h Access: RW, RO-V, RW-V...
  • Page 290 Processor Configuration Registers B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 108–10Fh Reset Value: 0000000000000000h Access: RW, RO-V, RW-V Size: 64 bits BIOS Optimal Default 0000000000000h Reset RST/ Attr Description Value IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field).