Rpga988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant) - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Figure 8-3.

rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)

V
VC C VC C VC C VC C
U
VC C VC C VC C VC C
T
VSS VSS VSS VSS
R
VC C VC C VC C VC C
P
VC C VC C VC C VC C
N
VSS VSS VSS VSS
PEG_R PEG_T PEG_T
M
VSS
X#[1] X[1] X#[1]
PEG_R PEG_R PEG_T
L
VSS
X[1] X#[2] X#[3]
PEG_R PEG_R
K
VSS VSS
X[2] X#[0]
PEG_R PEG_R PEG_R
J
VSS
X#[3] X[0] X#[4]
PEG_R PEG_R PEG_R
H
VSS
X[3] X#[5] X[4]
PEG_R PEG_R
G
VSS VSS
X[5] X#[7]
PEG_R PEG_R PEG_R
F
VSS
X#[9] X[7] X[11]
PEG_R PEG_R
PEG_R PEG_R
E
X#[10 X#[11
X[9] X[10]
]
PEG_R
PEG_R
D
VSS X#[12 VSS
X[12]
]
PEG_R
RSVD PEG_R
C
VSS X#[15
_NC TF X[14]
PEG_R
RSVD RSVD PEG_R
B
X#[14
_NC TF _NC TF X[15]
]
RSVD RSVD
A
VSS VSS
_NC TF _NC TF
35 34 33 32
110
VC C VC C VC C VC C
VC C VC C VC C VC C
VSS VSS VSS VSS
VC C VC C VC C VC C
VC C VC C VC C VC C
VSS VSS VSS VSS
PEG_T PEG_T PEG_T PEG_T
X#[2] X[2] X#[0] X[0]
PEG_T PEG_T PEG_T
VSS
X[3] X#[4] X[4]
PEG_T PEG_T PEG_T
VSS
X#[5] X[5] X#[6]
PEG_T PEG_T PEG_T
VSS
X#[7] X[7] X#[8]
PEG_R PEG_T PEG_T
VSS
X#[6] X#[9] X[9]
PEG_R PEG_R PEG_T
VSS
X[6] X#[8] X[10]
PEG_R PEG_T
VSS VSS
X[8] X[12]
PEG_T
PEG_R PEG_T
VSS X#[11
X[13] X[11]
] ]
PEG_R PEG_T
X#[13 RSVD VSS X#[13
] ]
VSS RSVD RSVD VSS
]
DMI_R
RSVD RSVD RSVD
X[0]
RSVD RSVD VSS BC LK
31 30 29 28
Processor Pin and Signal Information
VC C VC C
VC C VC C
VSS VSS
VC C VC C
VC C VC C
VSS VSS
VC C S VC C S
A A
VC C S
VSS
A
PEG_T
VSS
X[6]
PEG_T VC C S VC C S VC C S
X[8] A A A
VC C S VC C S
VSS VSS A_SEN
A A
PEG_T
X#[10 VSS RSVD RSVD
]
PEG_T PEG_T
X#[12 X#[14 RSVD RSVD RSVD
] ]
PEG_T
PEG_T
VSS X#[15 VSS
X[14]
]
PEG_T PEG_T
VSS RSVD RSVD
X[13] X[15]
PROC VC C S
VSS _SELE VSS A_VID
C T# [1]
DMI_R DMI_R DMI_R DMI_R DMI_R
X#[0] X[1] X#[1] X#[3]
BC LK DMI_R DMI_R
VSS
# X#[2] X[2]
27 26 25 24
PEG_I
VC C I PEG_I FDI0_
C OMP RSVD
O C OMPI LSYNC
O
VC C S PEG_R FDI0_
FDI_I
C OMP VSS TX#[1
NT
SE O
DMI_T DMI_T FDI0_
VSS VSS
X[0] X#[0] TX[1]
DMI_T DMI_T
VSS
X#[2] X[2]
FDI0_
DMI_T FDI0_
RSVD VSS TX#[2
X#[1] TX[2]
DMI_T DMI_T FDI1_
VSS
X[1] X#[3] TX[2]
VC C S FDI1_
DMI_T FDI1_
VSS A_VID TX#[1
X[3] TX[1]
[0] ]
FDI1_
FDI1_
VSS TX#[0
X[3] TX[0]
]
FDI0_
FDI0_
VSS TX#[0 VSS
TX[0] O_SEL
]
23 22 21 20
Datasheet, Volume 1
FDI0_
FSYNC
VSS
]
FDI0_
TX[3]
FDI0_
VSS TX#[3
]
VSS
]
FDI1_
TX#[2
]
eDP_T
X#[0]
VSS RSVD
VC C I eDP_C
OMPIO
19 18