Lcap-Link Capabilities Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.12.19 LCAP—Link Capabilities Register
This register indicates DMI specific capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:18
17:15
14:12
11:10
9:4
3:0
198
0/0/0/DMIBAR
84–87h
00012C41h
RW-O, RO, RW-OV
32 bits
00002h
Reset RST/
Attr
Value PWR
RO 0h
RW-O 010b Uncore
RW-O 010b Uncore
RO 11b Uncore
RO 04h Uncore
RW-OV 0001b Uncore
Processor Configuration Registers
Description
Reserved
L1 Exit Latency (L1SELAT)
This field indicates the length of time this Port requires to complete
the transition from L1 to L0. The value 010b indicates the range of
2 us to less than 4 us.
000 = Less than 1µs
001 = 1 µs to less than 2 µs
010 = 2 µs to less than 4 µs
011 = 4 µs to less than 8 µs
100 = 8 µs to less than 16 µs
101 = 16 µs to less than 32 µs
110 = 32 µs–64 µs
111 = More than 64 µs
Both bytes of this register that contain a portion of this field must
be written simultaneously in order to prevent an intermediate (and
undesired) value from ever existing.
L0s Exit Latency (L0SELAT)
This field indicates the length of time this Port requires to complete
the transition from L0s to L0.
000 = Less than 64 ns
001 = 64 ns to less than 128 ns
010 = 128 ns to less than 256 ns
011 = 256 ns to less than 512 ns
100 = 512 ns to less than 1 µs
101 = 1 µs to less than 2 µs
110 = 2 µs–4 µs
111 = More than 4 µs
Active State Link PM Support (ASLPMS)
L0s & L1 entry supported.
Max Link Width (MLW)
This field indicates the maximum number of lanes supported for
this link.
Max Link Speed (MLS)
This Reset Value reflects gen1.
0001 = 2.5 GT/s Link speed supported
0010 = 5.0 GT/s and 2.5 GT/s Link speeds supported
All other combinations are reserved.
Datasheet, Volume 2