Pcicmd-Pci Command Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.5.3 PCICMD—PCI Command Register
Since Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:10
9
8
7
6
5
4
3
Datasheet, Volume 2
0/0/0/PCI
4–5h
0006h
RO, RW
16 bits
00h
Reset RST/
Attr
Value PWR
RO 0h
RO 0b Uncore
RW 0b Uncore
RO 0b Uncore
RW 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0h
Description
Reserved
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast back-to-
back write. Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit position have
no effect.
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging. The
processor communicates the SERR condition by sending an SERR
message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over
DMI for specific Device 0 error conditions that are individually
enabled in the ERRCMD and DMIUEMSK registers. The error
status is reported in the ERRSTS, PCISTS, and DMIUEST
registers.
0 = The SERR message is not generated by the Host for Device 0.
This bit only controls SERR messaging for Device 0. Other
integrated devices have their own SERRE bits to control error
reporting for error conditions occurring in each device. The control
bits are used in a logical OR manner to enable the SERR DMI
message mechanism.
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled
Address/Data Stepping Enable (ADSTEP)
Address/data stepping is not implemented in the processor, and
this bit is hardwired to 0. Writes to this bit position have no effect.
Parity Error Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
0 = Disable. Master Data Parity Error bit in PCI Status register can
NOT be set.
1 = Enable. Master Data Parity Error bit in PCI Status register CAN
be set.
VGA Palette Snoop Enable (VGASNOOP)
The processor does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
Memory Write and Invalidate Enable (MWIE)
The processor will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0. Writes to this bit
position will have no effect.
Reserved
49