Memory Reference And Compensation; Memory Channel B - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Signal Description
Table 6-3.

Memory Channel B

Signal Name
SB_BS[2:0]
SB_WE#
SB_RAS#
SB_CAS#
SB_DQS[7:0]
SB_DQS#[7:0]
SB_DQ[63:0]
SB_MA[15:0]
SB_CK[1:0]
SB_CK#[1:0]
SB_CKE[1:0]
SB_CS#[1:0]
SB_ODT[1:0]
6.2

Memory Reference and Compensation

Table 6-4.

Memory Reference and Compensation

Signal Name
SM_RCOMP[2:0]
SM_VREF
Datasheet, Volume 1
Description
Bank Select: These signals define which banks are selected within
each SDRAM rank.
Write Enable Control Signal: This signal is used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
RAS Control Signal: This signal is used with SB_CAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
Data Strobes: SB_DQS[7:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SB_DQS[8:0] and its SB_DQS#[7:0] during read and write
transactions.
Data Bus: Channel B data signal interface to the SDRAM data bus.
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
SDRAM Differential Clock: Channel B SDRAM Differential clock signal
pair. The crossing of the positive edge of SB_CK and the negative edge
of its complement SB_CK# are used to sample the command and
control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel B SDRAM Differential
clock signal-pair complement.
Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR.
Chip Select: (1 per rank). These signals are used to select particular
SDRAM components during the active state. There is one Chip Select
for each SDRAM rank.
On Die Termination: Active Termination Control.
Description
System Memory Impedance Compensation:
DDR3 Reference Voltage: This provides reference voltage to the
DDR3 interface and is defined as V /2.
DDQ
Direction/
Buffer Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
Direction/
Buffer Type
I
A
I
A
79