Memory Remapping; Hardware Remap Algorithm; Programming Model - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.3.4.3

Memory Remapping

An incoming address (referred to as a logical address) is checked to see if it falls in the
memory re-map window. The bottom of the re-map window is defined by the value in
the REMAPBASE register. The top of the re-map window is defined by the value in the
REMAPLIMIT register. An address that falls within this window is remapped to the
physical memory starting at the address defined by the TOLUD register. The TOLUD
register must be 1 MB aligned.
2.3.4.4

Hardware Remap Algorithm

The following pseudo-code defines the algorithm used to calculate the DRAM address to
be used for a logical address above the top of physical memory made available using
re-claiming.
IF (ADDRESS_IN[38:20]  REMAP_BASE[35:20]) AND
(ADDRESS_IN[38:20]  REMAP_LIMIT[35:20]) THEN
ADDRESS_OUT[38:20] = (ADDRESS_IN[38:20] – REMAP_BASE[35:20]) +
0000000b and TOLUD[31:20]
ADDRESS_OUT[19:0] = ADDRESS_IN[19:0]
2.3.4.5

Programming Model

The memory boundaries of interest are:
• Bottom of Logical Address Remap Window defined by the REMAPBASE register,
which is calculated and loaded by BIOS.
• Top of Logical Address Remap Window defined by the REMAPLIMIT register, which
is calculated and loaded by BIOS.
• Bottom of Physical Remap Memory defined by the existing TOLUD register.
• Top of Physical Remap Memory, which is implicitly defined by either 4 GB or TOM
minus Manageability Engine stolen size.
Mapping steps:
1. Determine TOM
2. Determine TOM minus ME stolen size
3. Determine MMIO allocation
4. Determine TOLUD
5. Determine GFX stolen base
6. Determine GFX GTT stolen base
7. Determine TSEG base
8. Determine remap base/limit
9. Determine TOUUD
Figure 2-5
• Case 1: Less than 4 GB of Physical Memory, no remap
• Case 2: Greater than 4 GB of Physical Memory
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and Figure 2-6 show the two possible general cases of remapping.
Processor Configuration Registers
Datasheet, Volume 2