Cap_Reg-Capability Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.21.2 CAP_REG—Capability Register
This register reports general remapping hardware capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:56
55
54
53:48
47:40
39
38:38
37:34
33:24
Datasheet, Volume 2
0/0/0/VC0PREMAP
8–Fh
00C9008020660262h
RO
64 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RO 1b Uncore
RO 1b Uncore
RO 001001b Uncore
RO 00000000b Uncore
RO 1b Uncore
RO 0h
RO 0000b Uncore
RO 020h Uncore
Description
Reserved
DMA Read Draining (DRD)
0 = Hardware does Not support draining of DMA read requests.
1 = Hardware supports draining of DMA read requests.
DMA Write Draining (DWD)
0 = Hardware does Not support draining of DMA write requests.
1 = Hardware supports draining of DMA write requests.
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported value for
the Address Mask (AM) field in the Invalidation Address register
(IVA_REG) and IOTLB Invalidation Descriptor (iotlb_inv_dsc).
This field is valid only when the PSI field in Capability register is
reported as set.
Number of Fault-recording Registers (NFR)
Number of fault recording registers is computed as N+1, where N
is the value reported in this field.
Implementations must support at least one fault recording register
(NFR = 0) for each remapping hardware unit in the platform.
The maximum number of fault recording registers per remapping
hardware unit is 256.
Page Selective Invalidation (PSI)
0 = Hardware supports only domain and global invalidates for
IOTLB
1 = Hardware supports page selective, domain and global
invalidates for IOTLB
Hardware implementations reporting this field as set are
recommended to support a Maximum Address Mask Value (MAMV)
value of at least 9.
Reserved
Super-Page Support (SPS)
This field indicates the super page sizes supported by hardware.
A value of 1 in any of these bits indicates the corresponding super-
page size is supported. The super-page sizes corresponding to
various bit positions within this field are:
0h = 21-bit offset to page frame (2 MB)
1h = 30-bit offset to page frame (1 GB)
2h = 39-bit offset to page frame (512 GB)
3h = 48-bit offset to page frame (1 TB)
Hardware implementations supporting a specific super-page size
must support all smaller super-page sizes (that is, only valid
values for this field are 0001b, 0011b, 0111b, 1111b).
Fault-recording Register offset (FRO)
This field specifies the location to the first fault recording register
relative to the register base address of this remapping hardware
unit.
If the register base address is X, and the value reported in this
field is Y, the address for the first fault recording register is
calculated as X+(16*Y).
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