Table Of Contents - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

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Contents
1
Introduction ............................................................................................................ 11
1.1
Processor Feature Details ................................................................................... 13
1.1.1
Supported Technologies .......................................................................... 13
1.2
Interfaces ........................................................................................................ 13
1.2.1
System Memory Support ......................................................................... 13
1.2.2
PCI Express* ......................................................................................... 14
1.2.3
Direct Media Interface (DMI).................................................................... 15
1.2.4
Platform Environment Control Interface (PECI) ........................................... 16
1.2.5
Processor Graphics ................................................................................. 16
1.2.6
Embedded DisplayPort* (eDP*) ................................................................ 17
1.2.7
1.3
Power Management Support ............................................................................... 17
1.3.1
Processor Core....................................................................................... 17
1.3.2
System ................................................................................................. 17
1.3.3
Memory Controller.................................................................................. 17
1.3.4
PCI Express* ......................................................................................... 17
1.3.5
DMI...................................................................................................... 17
1.3.6
Processor Graphics Controller................................................................... 18
1.4
Thermal Management Support ............................................................................ 18
1.5
Package ........................................................................................................... 18
1.6
Terminology ..................................................................................................... 18
1.7
Related Documents ........................................................................................... 21
2
Interfaces................................................................................................................ 23
2.1
System Memory Interface .................................................................................. 23
2.1.1
System Memory Technology Supported ..................................................... 23
2.1.2
System Memory Timing Support............................................................... 24
2.1.3
System Memory Organization Modes......................................................... 24
2.1.3.1
2.1.3.2
2.1.4
Rules for Populating Memory Slots ............................................................ 25
2.1.5
Technology Enhancements of Intel
2.1.5.1
2.1.5.2
2.1.5.3
2.1.6
Memory Type Range Registers (MTRRs) Enhancement................................. 26
2.1.7
Data Scrambling .................................................................................... 26
2.1.8
DRAM Clock Generation........................................................................... 26
2.2
PCI Express* Interface....................................................................................... 27
2.2.1
PCI Express* Architecture ....................................................................... 27
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
PCI Express* Configuration Mechanism ..................................................... 29
2.2.3
PCI Express Graphics .............................................................................. 29
2.2.4
PCI Express Lanes Connection.................................................................. 30
2.3
Direct Media Interface (DMI)............................................................................... 30
2.3.1
DMI Error Flow....................................................................................... 30
2.3.2
Processor/PCH Compatibility Assumptions.................................................. 30
2.3.3
DMI Link Down ...................................................................................... 31
2.4
Processor Graphics Controller (GT) ...................................................................... 31
Datasheet, Volume 1
®
Single-Channel Mode................................................................. 24
Just-in-Time Command Scheduling.............................................. 26
Command Overlap .................................................................... 26
Out-of-Order Scheduling ............................................................ 26
Transaction Layer ..................................................................... 28
Data Link Layer ........................................................................ 28
Physical Layer .......................................................................... 28
®
FDI) ............................................. 17
®
®
Fast Memory Access (Intel
®
FMA).......... 26
3

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