Reset And Miscellaneous Signals; Pci Express* Based Interface Signals; Pci Express* Graphics Interface Signals - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

6.3

Reset and Miscellaneous Signals

Table 6-5.

Reset and Miscellaneous Signals

Signal Name
CFG[17:0]
PM_SYNC
RESET#
RSVD
RSVD_TP
RSVD_NCTF
SM_DRAMRST#
6.4

PCI Express* Based Interface Signals

Table 6-6.

PCI Express* Graphics Interface Signals

Signal Name
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX[15:0]
PEG_RX#[15:0]
PEG_TX[15:0]
PEG_TX#[15:0]
80
Configuration Signals: The CFG signals have a default value of '1' if not
terminated on the board.
• CFG[1:0]: Reserved configuration lane. A test point may be placed on
the board for this lane.
• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed
• CFG[3]: Reserved
• CFG[4]: eDP enable
— 1 = Disabled
— 0 = Enabled
• CFG[6:5]: PCI Express Bifurcation:
— 00 = 1 x8, 2 x4 PCI Express
— 01 = reserved
— 10 = 2 x8 PCI Express
— 11 = 1 x16 PCI Express
• CFG[17:7]: Reserved configuration lanes. A test point may be placed
on the board for these lands.
Power Management Sync: A sideband signal to communicate power
management status from the platform to the processor.
Platform Reset pin driven by the PCH
RESERVED: All signals that are RSVD and RSVD_NCTF must be left
unconnected on the board. However, Intel recommends that all RSVD_TP
signals have using test points.
DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One
common to all channels.
Description
PCI Express Input Current Compensation
PCI Express Current Compensation
PCI Express Resistance Compensation
PCI Express Receive Differential Pair
PCI Express Transmit Differential Pair
Description
Signal Description
Direction/
Buffer Type
I
CMOS
I
CMOS
I
CMOS
No Connect
Test Point
Non-Critical
to Function
O
CMOS
Direction/
Buffer Type
I
A
I
A
I
A
I
PCI Express
O
PCI Express
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