Ddr3 Signal Group Dc Specifications - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Electrical Specifications
Table 7-11. DDR3 Signal Group DC Specifications
Symbol Parameter
V Input Low Voltage
IL
V Input High Voltage
IH
V Input Low Voltage (SM_DRAMPWROK)
IL
V Input High Voltage (SM_DRAMPWROK)
IH
Output Low Voltage
V
OL
Output High Voltage
V
OH
R DDR3 Data Buffer pull-up Resistance
ON_UP(DQ)
R DDR3 Data Buffer pull-down Resistance
ON_DN(DQ)
DDR3 On-die termination equivalent
R
ODT(DQ) resistance for data signals
DDR3 On-die termination DC working
V
ODT(DC)
point (driver set to receive mode)
R DDR3 Clock Buffer pull-up Resistance
ON_UP(CK)
R DDR3 Clock Buffer pull-down Resistance
ON_DN(CK)
DDR3 Command Buffer pull-up
R
ON_UP(CMD)
Resistance
DDR3 Command Buffer pull-down
R
ON_DN(CMD)
Resistance
R DDR3 Control Buffer pull-up Resistance
ON_UP(CTL)
DDR3 Control Buffer pull-down
R
ON_DN(CTL)
Resistance
Input Leakage Current (DQ, CK)
0V
I 0.2*V
LI DDQ
0.8*V
DDQ
V
DDQ
Input Leakage Current (CMD, CTL)
0V
I 0.2*V
LI DDQ
0.8*V
DDQ
V
DDQ
SM_RCOMP0 Command COMP Resistance
SM_RCOMP1 Data COMP Resistance
SM_RCOMP2 ODT COMP Resistance
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
IL
value.
3. V is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
4. V and V
IH
signal quality specifications.
5. This is the pull up/down driver resistance.
6. R
TERM
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx resistors
are to V
9. DDR3 values are pre-silicon estimations and are subject to change.
10. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over V
edge must be monotonic.
11. SM_VREF is defined as V
Datasheet, Volume 1
SM_VREF + 0.1
V
DDQ
may experience excursions above V
OH
is the termination on the DIMM and in not controlled by the Processor.
.
SS
/2.
DDQ
Min Typ
— —
—
— —
*0.55 +0.1 —
(V / 2)* (R
DDQ
—
/(R +R
ON TERM
V - ((V / 2)*
— DDQ DDQ
(R /(R +R
ON ON TERM
24.31 28.6
22.88 28.6
83 100
41.5 50
0.43*V 0.5*V
CC CC
20.8 26
20.8 26
16 20
16 20
16 20
16 20
— —
— —
138.6 140
25.74 26
198 200
. However, input signal drivers must comply with the
DDQ
Max Units
SM_VREF -0.1 V
— V
V *0.55 -0.1 V
DDQ
— V
ON
—
))
— V
))
31.46 
34.32 
117

65
0.55*V V
CC
28.6 
31.2 
22 
24 
22 
24 
± 0.75
± 0.55 mA
± 0.9
± 1.4
± 0.85
± 0.65 mA
± 1.10
± 1.65
141.4 
26.26 
202 
±
* 0.55 200 mV and the
DDQ
1
Notes
2, 4, 11
3, 11
10
10
6
4, 6
5
5
5
5
5
5
5
5
8
8
8
101