Lctl-Link Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.10.38 LCTL—Link Control Register
This register allows control of PCI Express link.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:12
11
10
9
8
7
Datasheet, Volume 2
0/6/0/PCI
B0–B1h
0000h
RO, RW, RW-V
16 bits
00h
Reset RST/
Attr
Value PWR
RO 0h
RW 0b Uncore
RW 0b Uncore
RW 0b Uncore
RO 0b Uncore
RW 0b Uncore
Description
Reserved
Link Autonomous Bandwidth Interrupt Enable (LABIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Autonomous Bandwidth Status bit has been
Set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification
capability must hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable (LBMIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Bandwidth Management Status bit has been
Set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Hardware Autonomous Width Disable (HAWD)
When Set, this bit disables hardware from changing the Link width
for reasons other than attempting to correct unreliable Link
operation by reducing Link width.
Devices that do not implement the ability autonomously to change
Link width are permitted to hardwire this bit to 0b.
Enable Clock Power Management (ECPM)
Applicable only for form factors that support a "Clock Request"
(CLKREQ#) mechanism, this enable functions as follows:
0 = Clock power management is disabled and device must hold
CLKREQ# signal low
1 = Device is permitted to use CLKREQ# signal to power manage
link clock according to protocol defined in appropriate form
factor specification.
Components that do not support Clock Power Management (as
indicated by a 0b value in the Clock Power Management bit of the
Link Capabilities Register) must hardwire this bit to 0b.
Extended Synch (ES)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
exiting the L0s state and when in the Recovery state.
This mode provides external devices (such as logic analyzers)
monitoring the Link time to achieve bit and symbol lock before the
link enters L0 and resumes communication.
This is a test mode only and may cause other undesired side
effects such as buffer overflows or underruns.
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