Ground And Nctf; Future Compatibility; Processor Internal Pull Up/Pull Down - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Signal Description
6.14

Ground and NCTF

Table 6-16. Ground and NCTF
Signal Name
VSS
VSS_NCTF
(BGA Only)
DC_TEST_xx#
6.15

Future Compatibility

Table 6-17. Future Compatibility
Signal Name
PROC_SELECT#
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VCCIO_SEL
VCCSA_VID[0]
6.16

Processor Internal Pull Up/Pull Down

Table 6-18. Processor Internal Pull Up/Pull Down
Signal Name
BPM[7:0]
PRDY#
PREQ#
TRST#
CFG[17:0]
Datasheet, Volume 1
Processor ground node
Non-Critical to Function: These pins are for package mechanical
reliability.
Daisy Chain- These pins are for solder joint reliability and non-critical to
function. For BGA only.
This pin is for compatibility with future platforms. A pull-up resistor
to V is required if connected to the DF_TVS strap on the PCH.
CPLL
Memory Channel A/B DIMM DQ Voltage Reference: These
signals are not used by the processors and are for future compatibility
only. No connection is required.
Voltage selection for VCCIO: This pin must be pulled high on the
motherboard, when using dual rail voltage regulator, which will be
used for future compatibility.
Voltage selection for VCCSA: This pin must have a pull down
resistor to ground.
Pull Up/Pull Down
Pull Up
Pull Up
Pull Up
TCK Pull Down
TDI Pull Up
TMS Pull Up
Pull Up
Pull Up
Description
Description
Rail
VCCIO
VCCIO
VCCIO
VSS
VCCIO
VCCIO
VCCIO
VCCIO
§ §
Direction/
Buffer Type
GND
Direction/
Buffer Type
Value
65–165 
65–165 
65–165 
5–15 k
5–15 k
5–15 k
5–15 k
5–15 k
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