Pxpepbar; Epvc0Rctl-Ep Vc 0 Resource Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.20

PXPEPBAR

Table 2-22
the sections following the table.
Table 2-22. PXPEPBAR Register Address Map
Address
Offset
0–13h
14–17h
18–9F
2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register
This register controls the resources associated with Egress Port Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:20
19:17
16:0
258
lists the registers arr anged by address offset. Register bit descriptions are in
Register
Symbol
RSVD Reserved
EPVC0RCTL EP VC 0 Resource Control
RSVD Reserved
0/0/0/PXPEPBAR
14–17h
800000FFh
RO, RW
32 bits
00000h
Reset RST/
Attr
Value PWR
RO 0h
RW 000b Uncore
RO 0h
Processor Configuration Registers
Register Name
Description
Reserved
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. The value of 0h corresponds to the bit position
of the only asserted bit in the Port Arbitration Capability field.
Reserved
Reset Value Access
0h RO
800000FFh RO, RW
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Datasheet, Volume 2