Signal Groups; Signal Groups1 - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Electrical Specifications
7.6

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals, have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Table 7-3. Signal Groups
Signal Group
System Reference Clock
Differential
DDR3 Reference Clocks
Differential
DDR3 Command Signals
Single Ended
DDR3 Control Signals
Single Ended
DDR3 Data Signals
Single ended
Differential
DDR3 Compensation
DDR3 Reference
TAP (ITP/XDP)
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Control Sideband
Single Ended
Datasheet, Volume 1
1
(Sheet 1 of 3)
Type
CMOS Input
2
DDR3 Output
2
DDR3 Output
2
DDR3 Output
2
DDR3 Bi-directional
DDR3 Bi-directional
Analog Bi-directional
Analog Input
Output
CMOS Input
Open-Drain Output
Output
Asynchronous CMOS
Bi-Directional
Asynchronous CMOS
Input
Asynchronous CMOS
Output
CMOS Input
Signals
BCLK, BCLK#
DPLL_REF_CLK, DPLL_REF_CLK#
SA_CK[1:0], SA_CK#[1:0]
SB_CK[1:0], SB_CK#[1:0]
SA_BS[2:0], SB_BS[2:0]
SA_WE#, SB_WE#
SA_RAS#, SB_RAS#
SA_CAS#, SB_CAS#
SA_MA[15:0], SB_MA[15:0]
SA_CKE[1:0], SB_CKE[1:0]
SA_CS#[1:0], SB_CS#[1:0]
SA_ODT[1:0], SB_ODT[1:0]
SM_DRAMRST#
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[7:0], SA_DQS#[7:0]
SB_DQS[7:0], SB_DQS#[7:0]
SM_RCOMP[2:0]
SM_VREF
BCLK_ITP, BCLK_ITP#
TCK, TDI, TMS, TRST#
TDO
DBR#
BPM#[7:0]
PREQ#
PRDY#
CFG[17:0]
Table 7-3. The
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