Dc Characteristics; Input Device Hysteresis; Peci Dc Electrical Limits - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

Electrical Specifications
7.11.2

DC Characteristics

The PECI interface operates at a nominal voltage set by V
specifications shown in
interface supply. V
devices will operate at the V
system. For specific nominal V
Table 7-11. PECI DC Electrical Limits
Symbol
Rup
V
in
V
hysteresis
V
n
V
p
C
bus
Cpad
Ileak000
Ileak025
Ileak050
Ileak075
Ileak100
Notes:
1. V
CCIO
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull up resistance measured at 0.75*V
7.11.3

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 7-2.

Input Device Hysteresis

V
TTD
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
Datasheet, Volume 1
Table 7-11
nominal levels will vary between processor families. All PECI
CCIO
CCIO
CCIO
Definition and Conditions
Internal pull up resistance
Input Voltage Range
Hysteresis
Negative-Edge Threshold Voltage
Positive-Edge Threshold Voltage
Bus Capacitance per Node
Pad Capacitance
leakage current at 0V
leakage current at 0.25*V
leakage current at 0.50*V
leakage current at 0.75*V
leakage current at V
CCIO
supplies the PECI interface. PECI behavior does not affect V
PECI High Range
P
P
N
PECI Low Range
N
is used with devices normally operating from a V
level determined by the processor installed in the
levels, refer to Table
Min
15
-0.15
0.1 * V
CCIO
0.275 * V
CCIO
0.550 * V
CCIO
N/A
0.7
—
—
CCIO
—
CCIO
—
CCIO
—
CCIO
Figure 7-2 as a guide for input buffer design.
§ §
. The set of DC electrical
CCIO
7-6.
Max Units
45 Ohm
V V
CCIO
N/A V
0.500 * V V
CCIO
0.725 * V V
CCIO
10 pF
1.8 pF
0.6 mA
0.4 mA
0.2 mA
0.13 mA
0.10 mA
min/max specifications.
CCIO
Minimum Valid Input
Hysteresis Signal Range
CCIO
1
Notes
3
2
2
2
2
2
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