Mchbar Registers In Memory Controller - Channel 1; Pm_Pdwn_Config_C1-Power-Down Configuration Register; Mchbar Registers In Memory Controller - Channel 1 Register Address Map - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.14 MCHBAR Registers in Memory Controller –
Channel 1
Table 2-16
the sections following the table.
Table 2-16. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map
Address
Offset
0–44C7h
44B0-44B3h
0–44C7h
44D0–4693h
4694–4697h
4698–469Bh
469C–438Fh
2.14.1 PM_PDWN_Config_C1—Power-down Configuration
Register
This register defines the power-down (CKE-off) operation – power-down mode, idle
timer, and global / per rank decision.
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default:
Bit
31:13
12
11:8
7:0
206
lists the registers arr anged by address offset. Register bit descriptions are in
Register Symbol
RSVD Reserved
PM_PDWN_Config_C1 Power-down Configuration
RSVD Reserved
RSVD Reserved
TC_RFP_C1 Refresh Parameters
TC_RFTP_C1 Refresh Parameters
RSVD Reserved
0/0/0/MCHBAR MC1
44B0-44B3h
00000000h
RW-L
32 bits
00000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 0b Uncore
RW-L 0h Uncore
RW-L 00h Uncore
Processor Configuration Registers
Register Name
Description
Reserved
Global power-down (GLPDN)
1 = Power-down decision is global for channel.
0 = A separate decision is taken for each rank.
Power-down mode (PDWN_mode)
Selects the mode of power-down. All encodings not in table are
reserved.
Note: When selecting DLL-off or APD-DLL off, DIMM MR0 register
bit 12 (PPD) must equal 0.
Note: When selecting APD, PPD or APD-PPD, DIMM MR0 register
bit 12 (PPD) must equal 1.
The value 0h (no power-down) is a don't care.
0h = No Power Down
1h = APD
2h = PPD
3h = APD - PPD
6h = DLL Off
7h = APD - DLL Off
Power-down idle timer (PDWN_idle_counter)
This defines the rank idle period in DCLK cycles that causes power-
down entrance.
Reset
Access
Value
— —
00000000h RW-L
— —
— —
0000980Fh RW-L
46B41004h RW-L
— —
Datasheet, Volume 2