Pm_Cs6-Power Management Control/Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.10.26 PM_CS6—Power Management Control/Status Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:16
15
14:13
12:9
8
7:4
3
2
Datasheet, Volume 2
0/6/0/PCI
84–87h
00000008h
RO, RW
32 bits
000000h
Reset RST/
Attr
Value PWR
RO 0h
RO 0b Uncore
RO 00b Uncore
RO 0h Uncore
RW 0b Uncore
RO 0h
RO 1b Uncore
RO 0h
Description
Reserved
PME Status (PMESTS)
This bit indicates that this device does not support PME#
generation from D3cold.
Data Scale (DSCALE)
This field indicates that this device does not support the power
management data register.
Data Select (DSEL)
This field indicates that this device does not support the power
management data register.
PME Enable (PMEE)
This bit indicates that this device does not generate PME#
assertion from any D-state.
0 = Disable. PME# generation not possible from any D State
1 = Enable. PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
Reserved
No Soft Reset (NSR)
1 = Device is transitioning from D3hot to D0 because the power
state commands do not perform an internal reset.
Configuration context is preserved. Upon transition, no
additional operating system intervention is required to
preserve configuration context beyond writing the power state
bits.
0 = Devices do not perform an internal reset upon transitioning
from D3hot to D0 using software control of the power state
bits.
Regardless of this bit, the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device state
D0 uninitialized with only PME context preserved if PME is
supported and enabled.
Reserved
163