Lctl-Link Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.12.20 LCTL—Link Control Register
This register allows control of PCI Express link.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:10
9
8:8
7
6:6
5
4:2
1:0
Datasheet, Volume 2
0/0/0/DMIBAR
88–89h
0000h
RW, RW-V
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RW 0b Uncore
RO 0h
RW 0b Uncore
RO 0h
RW-V 0b Uncore
RO 0h
RW 00b Uncore
Description
Reserved
Hardware Autonomous Width Disable (HAWD)
When set, this bit disables hardware from changing the Link width
for reasons other than attempting to correct unreliable Link
operation by reducing Link width.
Devices that do not implement the ability autonomously to change
Link width are permitted to hardwire this bit to 0b.
Reserved
Extended Synch (ES)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
exiting the L0s state and when in the Recovery state.
This mode provides external devices (such as, logic analyzers)
monitoring the Link time to achieve bit and symbol lock before the
link enters L0 and resumes communication.
This is a test mode only and may cause other undesired side
effects such as buffer overflows or underruns.
Reserved
Retrain Link (RL)
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer
TXTSSM from L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
Reserved
Active State PM (ASPM):
This field controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
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