Ssts1-Secondary Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.6.14 SSTS1—Secondary Status Register
SSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI
bridge embedded within the processor.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15
14
13
12
11
10:9
8
7
6:6
5
4:0
Datasheet, Volume 2
0/1/0–2/PCI
1E–1Fh
0000h
RW1C, RO
16 bits
00h
Reset RST/
Attr
Value PWR
RW1C 0b Uncore
RW1C 0b Uncore
RW1C 0b Uncore
RW1C 0b Uncore
RO 0b Uncore
RO 00b Uncore
RW1C 0b Uncore
RO 0b Uncore
RO 0h
RO 0b Uncore
RO 0h
Description
Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration
Space header device whenever it receives a Poisoned TLP,
regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration
space header device receives an ERR_FATAL or ERR_NONFATAL.
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Unsupported Request
Completion Status.
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Completer Abort
Completion Status.
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The processor
does not generate Target Aborts (The root port will never complete
a request using the Completer Abort Completion status).
UR detected inside the processor (such as in /MC will be reported
in primary side status)
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
Master Data Parity Error (SMDPE)
When set, this bit indicates that the processor received across the
link (upstream) a Read Data Completion Poisoned TLP (EP=1). This
bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
Reserved
93