Ecap_Reg-Extended Capability Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.21.3 ECAP_REG—Extended Capability Register
This register reports remapping hardware extended capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:24
23:20
19:18
17:8
7
6
5
4
3
264
0/0/0/VC0PREMAP
10–17h
0000000000F010DAh
RO-V, RO
64 bits
00000000000h
Reset RST/
Attr
Value PWR
RO 0h
RO 1111b Uncore
RO 0h
RO 010h Uncore
RO-V 1b Uncore
RO-V 1b Uncore
RO 0b Uncore
RO-V 1b Uncore
RO-V 1b Uncore
Processor Configuration Registers
Description
Reserved
Maximum Handle Mask Value (MHMV)
The value in this field indicates the maximum supported value for
the Handle Mask (HM) field in the interrupt entry cache invalidation
descriptor (iec_inv_dsc).
This field is valid only when the IR field in Extended Capability
register is reported as set.
Reserved
IOTLB Register Offset (IRO)
This field specifies the offset to the IOTLB registers relative to the
register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field
is Y, the address for the first IOTLB invalidation register is
calculated as X+(16*Y).
Snoop Control (SC)
0 = Hardware does not support 1-setting of the SNP field in the
page-table entries.
1 = Hardware supports the 1-setting of the SNP field in the page-
table entries.
Pass Through (PT):
0 = Hardware does not support pass-through translation type in
context entries.
1 = Hardware supports pass-through translation type in context
entries.
Caching Hints (CH):
0 = Hardware does not support IOTLB caching hints (ALH and EH
fields in context-entries are treated as reserved).
1 = Hardware supports IOTXTB caching hints through the ALH and
EH fields in context-entries.
Extended Interrupt Mode (EIM)
0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs
(xAPIC mode).
1 = On Intel 64 platforms, hardware supports 32-bit APIC-IDs
(x2APIC mode).
This field is valid only on Intel 64 platforms reporting Interrupt
Remapping support (IR field Set).
Interrupt Remapping Support (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as set must also support
Queued Invalidation (QI).
Datasheet, Volume 2