Ieuaddr_Reg-Invalidation Event Upper Address Register; Irta_Reg-Interrupt Remapping Table Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.21.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
2.21.27 IRTA_REG—Interrupt Remapping Table Address Register
This register provides the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:39
38:12
11
10:4
3:0
Datasheet, Volume 2
0/0/0/VC0PREMAP
AC–AFh
00000000h
RW-L
32 bits
Reset RST/
Attr
Value PWR
RW-L 00000000h Uncore
0/0/0/VC0PREMAP
B8–BFh
0000000000000000h
RW-L
64 bits
00000000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 0000000h Uncore
RW-L 0b Uncore
RO 0h
RW-L 0h Uncore
Description
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and
Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or
Extended Interrupt Mode may treat this field as RsvdZ.
Description
Reserved
Interrupt Remapping Table Address (IRTA)
This field points to the base of 4KB aligned interrupt remapping
table.
Hardware ignores and does not implement bits 63:HAW, where
HAW is the host address width.
Reads of this field returns value that was last programmed to it.
Extended Interrupt Mode Enable (EIME)
This field is used by hardware on Intel 64 platforms as follows:
0 = xAPIC mode is active. Hardware interprets only low 8-bits of
Destination-ID field in the IRTEs. The high 24-bits of the
Destination-ID field are treated as reserved.
1 = x2APIC mode is active. Hardware interprets all 32-bits of
Destination-ID field in the IRTEs.
This field is implemented as RsvdZ on implementations reporting
Extended Interrupt Mode (EIM) field as Clear in Extended
Capability register.
Reserved
Size (S)
This field specifies the size of the interrupt remapping table. The
number of entries in the interrupt remapping table is 2^(X+1),
where X is the value programmed in this field.
287