Intel Core i7 Mobile Extreme Edition Series Manuals

Manuals and User Guides for Intel Core i7 Mobile Extreme Edition Series. We have 1 Intel Core i7 Mobile Extreme Edition Series manual available for free PDF download: Datasheet

INTEL Core i7 Mobile Extreme Edition Series Datasheet

INTEL Core i7 Mobile Extreme Edition Series Datasheet (172 pages)

Brand: INTEL | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
3
Revision History
10
1 Introduction

11
- 2Nd Generation Intel Platform
  12
  - Processor Feature Details
    13
    
    Supported Technologies
    13
  - Interfaces
    13
    
    System Memory Support
    13
    
    PCI Express
    14
- Pcie Supported Configurations in Mobile Products
  14
  - Direct Media Interface (DMI)
    15
  - Platform Environment Control Interface (PECI)
    16
  - Processor Graphics
    16
  - Embedded Displayport* (Edp*)
    17
  - Intel ® Flexible Display Interface (Intel ® FDI)
    17
  - Power Management Support
    17
    
    DMI
    17
    
    Memory Controller
    17
    
    PCI Express
    17
    
    Processor Core
    17
    
    System
    17
    
    Processor Graphics Controller
    18
  - Thermal Management Support
    18
  - Package
    18
  - Terminology
    18
  - Related Documents
    21
2 Interfaces

23
- System Memory Interface
  23
  - System Memory Technology Supported
    23
- Supported SO-DIMM Module Configurations 1,2
  23
  - System Memory Timing Support
    24
  - System Memory Organization Modes
    24
    
    Dual-Channel Mode - Intel ® Flex Memory Technology Mode
    24
    
    Single-Channel Mode
    24
- DDR3 System Memory Timing Support
  24
  - Rules for Populating Memory Slots
    25
- Intel ® Flex Memory Technology Operation
  25
  - Fma)
    26
  - Just-In-Time Command Scheduling
    26
  - Command Overlap
    26
  - Out-Of-Order Scheduling
    26
  - Memory Type Range Registers (Mtrrs) Enhancement
    26
  - Data Scrambling
    26
  - DRAM Clock Generation
    26
  - PCI Express* Interface
    27
    
    PCI Express* Architecture
    27
- PCI Express* Layering Diagram
  27
  - Transaction Layer
    28
  - Data Link Layer
    28
  - Physical Layer
    28
- Packet Flow through the Layers
  28
  - PCI Express* Configuration Mechanism
    29
  - PCI Express Graphics
    29
- PCI Express* Related Register Structures in the Processor
  29
  - PCI Express Lanes Connection
    30
  - Direct Media Interface (DMI)
    30
    
    DMI Error Flow
    30
    
    Processor/Pch Compatibility Assumptions
    30
- Pcie Typical Operation 16 Lanes Mapping
  30
  - DMI Link down
    31
  - Processor Graphics Controller (GT)
    31
- Processor Graphics Controller Unit Block Diagram
  31
  - 3D and Video Engines for Graphics Processing
    32
    
    3D Engine Execution Units
    32
    
    3D Pipeline
    32
    
    Engine
    33
    
    Video Engine
    33
    
    Display Planes
    34
    
    Processor Graphics Display
    34
- Processor Display Block Diagram
  34
- Reference Clock
  36
3 Technologies

37
4 Power Management

45
- ACPI States Supported
  45
  - System States
    45
  - Processor Core/Package Idle States
    45
- Processor Core/Package State Support
  45
  - Integrated Memory Controller States
    46
  - Pcie Link States
    46
  - DMI States
    46
  - Processor Graphics Controller States
    46
  - Interface State Combinations
    47
- G, S, and C State Combinations
  47
- D, S, and C State Combination
  47
  - Processor Core Power Management
    48
    
    Enhanced Intel ® Speedstep ® Technology
    48
    
    Low-Power Idle States
    48
- Idle Power Management Breakdown of the Processor Cores
  49
- Thread and Core C-State Entry and Exit
  49
  - Requesting Low-Power Idle States
    50
- Coordination of Thread Power States at the Core Level
  50
- P_Lvlx to MWAIT Conversion
  50
  - Core C-States
    51
    
    Core C0 State
    51
    
    Core C1/C1E State
    51
    
    Core C3 State
    51
    
    Core C6 State
    51
    
    Core C7 State
    51
    
    C-State Auto-Demotion
    52
    
    Package C-States
    52
    
    Package C0
    53
- Package C-State Entry and Exit
  53
- Coordination of Core Power States at the Package Level
  53
  - Package C1/C1E
    54
  - Package C3 State
    54
  - Package C6 State
    54
  - Package C7 State
    55
  - Dynamic L3 Cache Sizing
    55
  - IMC Power Management
    55
    
    Disabling Unused System Memory Outputs
    55
    
    DRAM Power Management and Initialization
    56
    
    Conditional Self-Refresh
    57
    
    Initialization Role of CKE
    57
    
    DRAM I/O Power Management
    58
    
    Dynamic Power-Down Operation
    58
  - Pcie* Power Management
    58
  - DMI Power Management
    58
- Targeted Memory State Conditions
  58
  - Graphics Power Management
    59
    
    Graphics Performance Modulation Technology(GPMT)
    59
    
    Graphics Render C-State
    59
    
    Intel
    59
    
    Intel Smart 2D Display Technology (Intel S2DDT)
    59
    
    Automatic Display Brightness (ADB)
    60
    
    Display Power Savings Technology 6.0 (DPST)
    60
    
    Intel Graphics Dynamic Frequency
    60
    
    Seamless Display Refresh Rate Switching Technology (SDRRST)
    61
  - Thermal Power Management
    61
5 Thermal Management

63
6 Signal Description

77
- Signal Description Buffer Types
  77
  - System Memory Interface
    78
- Memory Channel a
  78
  - Memory Reference and Compensation
    79
- Memory Channel B
  79
  - Reset and Miscellaneous Signals
    80
  - PCI Express* Based Interface Signals
    80
- PCI Express* Graphics Interface Signals
  80
  - Embedded Displayport (Edp)
    81
  - Intel ® Flexible Display Interface Signals
    81
  - DMI
    81
- Embedded Display Port Signals
  81
- Intel® Flexible Display Interface
  81
- DMI - Processor to PCH Serial Interface
  81
  - PLL Signals
    82
  - TAP Signals
    82
  - Error and Thermal Protection
    83
  - Power Sequencing
    83
  - Processor Power Signals
    84
  - Sense Pins
    84
  - Ground and NCTF
    85
  - Future Compatibility
    85
  - Processor Internal Pull Up/Pull down
    85
7 Electrical Specifications

87
8 Processor Pin and Signal Information

107
9 DDR Data Swizzling

169
- DDR Data Swizzling Table - Channel a
  170
- DDR Data Swizzling Table - Channel B
  171

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