Signal Groups; Signal Groups 1 - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

Electrical Specifications
7.7

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Table 7-3. Signal Groups (Sheet 1 of 2)
Signal Group
System Reference Clock
Differential
DDR3 Reference Clocks
Differential
DDR3 Command Signals
Single Ended
DDR3 Data Signals
Single ended
Differential
TAP (ITP/XDP)
Single Ended
Single Ended
Single Ended
Control Sideband
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Power/Ground/Other
Datasheet, Volume 1
1
Type
CMOS Input
2
DDR3 Output
2
DDR3 Output
2
DDR3 Bi-directional
DDR3 Bi-directional
CMOS Input
CMOS Output
Asynchronous CMOS Output
CMOS Input
Asynchronous CMOS/Open
Drain Bi-directional
Asynchronous CMOS Output
Asynchronous CMOS Input
Asynchronous Bi-directional
CMOS Input
Open Drain Output
Bi-directional CMOS Input
/Open Drain Output
Power
Ground
No Connect and test point
Signals
BCLK[0], BCLK#[0]
SA_CK[3:0], SA_CK#[3:0]
SB_CK[3:0], SB_CK#[3:0]
SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
SM_DRAMRST#
SA_CS#[3:0], SB_CS#[3:0]
SA_ODT[3:0], SB_ODT[3:0]
SA_CKE[3:0], SB_CKE[3:0]
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[8:0], SA_DQS#[8:0]
SB_DQS[8:0], SB_DQS#[8:0]
TCK, TDI, TMS, TRST#
TDO
TAPPWRGOOD
CFG[17:0]
PROCHOT#
THERMTRIP#, CATERR#
SM_DRAMPWROK, UNCOREPWRGOOD
RESET#
PECI
VIDALERT#
VIDSCLK
VIDSOUT
VCC, VCC_NCTF, VCCIO, VCCPLL, VDDQ, VCCAXG
V
SS
RSVD, RSVD_NCTF, RSVD_TP, FC_x
Table 7-3. The
3
, PM_SYNC,
75