Pcists6-Pci Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.10.4 PCISTS6—PCI Status Register
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the Root port.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15
14
13
12
11
10:9
146
0/6/0/PCI
6–7h
0010h
RW1C, RO, RO-V
16 bits
0h
Reset RST/
Attr
Value PWR
RW1C 0b Uncore
RW1C 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 00b Uncore
Processor Configuration Registers
Description
Detected Parity Error (DPE)
This bit is set by a Function when it receives a Poisoned TLP,
regardless of the state the Parity Error Response bit in the
Command register. On a Function with a Type 1 Configuration
header, the bit is set when the Poisoned TLP is received by its
Primary Side.
This bit will be set only for completions of requests encountering
ECC error in DRAM.
Poisoned Peer-to-peer posted forwarded will not set this bit. They
are reported at the receiving port.
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting an
ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in
the Command register is 1. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect
this field.
Received Master Abort Status (RMAS)
This bit is set when a Requester receives a Completion with
Unsupported Request Completion Status. On a Function with a
Type 1 Configuration header, the bit is set when the Unsupported
Request is received by its Primary Side.
Not applicable. There is not a UR on the primary interface
Received Target Abort Status (RTAS)
This bit is set when a Requester receives a Completion with
Completer Abort Completion Status. On a Function with a Type
Configuration header, the bit is set when the Completer Abort is
received by its Primary Side.
Not Applicable or Implemented. Hardwired to 0. The concept of a
Completer abort does not exist on primary side of this device.
Signaled Target Abort Status (STAS)
This bit is set when a Function completes a Posted or Non
Request as a Completer Abort error. This applies to a Function with
a Type 1 Configuration header when the Completer Abort was
generated by its Primary Side.
Not Applicable or Implemented. Hardwired to 0. The concept of a
target abort does not exist on primary side of this device.
DEVSELB Timing (DEVT)
This device is not the subtractive decoded device on bus 0. This bit
field is therefore hardwired to 00 to indicate that the device uses
.
the fastest possible decode
Does not apply to PCI Express and must be hardwired to 00b.
1
-
Posted
Datasheet, Volume 2