Pci Device 2 Configuration Space; Pci Device 2 Configuration Register Address Map - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.8

PCI Device 2 Configuration Space

Table 2-10
the sections following the table.
Table 2-10. PCI Device 2 Configuration Register Address Map
Address
Offset
0–1h
2–3h
4–5h
6–7h
8h
9–Bh
Ch
Dh
Eh
Fh
10–17h
18–1Fh
20–23h
24–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–3Bh
3Ch
3Dh
3Eh
3Fh
40–61h
62–62h
63–FFh
128
lists the registers arr anged by address offset. Register bit descriptions are in
Register
Symbol
VID2 Vendor Identification
DID2 Device Identification
PCICMD2 PCI Command
PCISTS2 PCI Status
RID2 Revision Identification
CC Class Code
CLS Cache Line Size
MTXT2 Master Latency Timer
HDR2 Header Type
RSVD Reserved
Graphics Translation Table, Memory Mapped Range
GTTMMADR
Address
Graphics Memory Range Address
GMADR
IOBAR I/O Base Address
RSVD Reserved
SVID2 Subsystem Vendor Identification
SID2 Subsystem Identification
ROMADR Video BIOS ROM Base Address
RSVD Reserved
RSVD Reserved
RSVD Reserved
INTRPIN Interrupt Pin
MINGNT Minimum Grant
MAXLAT Maximum Latency
RSVD Reserved
MSAC Multi Size Aperture Control
RSVD Reserved
Processor Configuration Registers
Register Name
Reset
Access
Value
8086h RO
0102h RO-V, RO-FW
0000h RW, RO
0090h RO, RO-V
00h RO-FW
030000h RO-V, RO
00h RO
00h RO
00h RO
0h RO
000000000
RW, RO
0000004h
000000000 RO, RW-L,
000000Ch RW
00000001h RW, RO
0h RO
0000h RW-O
0000h RW-O
00000000h RO
90h RO-V
0h RO
00h RW
01h RO
00h RO
00h RO
— —
02h RW, RW-K
— —
Datasheet, Volume 2