Ggc-Gmch Graphics Control Register Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.5.12 GGC—GMCH Graphics Control Register Register
All the bits in this register are Intel TXT lockable.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:15
14
13:10
9:8
Datasheet, Volume 2
0/0/0/PCI
50–51h
0028h
RW-KL, RW-L
16 bits
00h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 0b Uncore
RO 0h
RW-L 0h Uncore
Description
Reserved
Versatile Acceleration Mode Enable (VAMEN)
Enables the use of the iGFX enable for Versatile Acceleration.
1 = iGFX engines are in Versatile Acceleration Mode. Device 2
Class Code is 048000h.
0 = iGFX engines are in iGFX Mode. Device 2 Class Code is
030000h.
Reserved
GTT Graphics Memory Size (GGMS)
This field is used to select the amount of Main Memory that is pre-
allocated to support the Internal Graphics Translation Table. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space with
DSM, and BIOS needs to allocate a contiguous memory chunk.
Hardware will derive the base of GSM from DSM only using the
GSM size programmed in the register.
Hardware functionality in case of programming this value to
Reserved is not ensured.
Encoding:
1h = 1 MB of pre-allocated memory
2h = 2 MB of pre-allocated memory
3h = Reserved
0h = No pre-allocated memory
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