Intrpin1-Interrupt Pin Register; Bctrl1-Bridge Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.23 INTRPIN1—Interrupt Pin Register
This register specifies which interrupt pin this device uses.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:3
2:0
2.6.24 BCTRL1—Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-to-PCI
bridges. BCTRL1 provides additional control for the secondary interface (that is, PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within the processor (such as, VGA compatible address
ranges mapping).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:12
11
10
9
8
7
100
0/1/0–2/PCI
3Dh
01h
RW-O, RO
8 bits
Reset RST/
Attr
Value PWR
RO 00h Uncore
RW-O 1h Uncore
0/1/0–2/PCI
3E–3Fh
0000h
RW, RO
16 bits
0h
Reset RST/
Attr
Value PWR
RO 0h
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
Processor Configuration Registers
Description
Interrupt Pin High (INTPINH)
Interrupt Pin (INTPIN)
As a multifunction device, the PCI Express device may specify any
INTx (x=A, B, C, D) as its interrupt pin.
The Interrupt Pin register tells which interrupt pin the device (or
device function) uses.
1h = Corresponds to INTA# (Default)
2h = Corresponds to INTB#
3h = Corresponds to INTC#
4h = Corresponds to INTD#
05h–FFh = Reserved.
Devices (or device functions) that do not use an interrupt pin must
put a 0 in this register.
This register is write once. BIOS must set this register to select the
INTx to be used by this root port.
Description
Reserved
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hardwired to 0.
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hardwired to 0.
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hardwired to 0
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
.
Datasheet, Volume 2