2.10.10
SBUSN6—Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.10.11
SUBUSN6—Subordinate Bus Number Register
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
150
0/6/0/PCI
19h
00h
RW
8 bits
Reset
RST/
Attr
Value
PWR
RW
00h
Uncore
0/6/0/PCI
1Ah
00h
RW
8 bits
Reset
RST/
Attr
Value
PWR
RW
00h
Uncore
Processor Configuration Registers
Description
Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
Description
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the
processor root port bridge. When only a single PCI device resides
on the PCI Express-G segment, this register will contain the same
value as the SBUSN1 register.
Datasheet, Volume 2