Touud-Top Of Upper Usable Dram Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.5.27 TOUUD—Top of Upper Usable DRAM Register
This 64-bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all ME stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit +
1 byte, 1 M B aligned, s ince reclaim limit is 1 MB aligned. Address bits 19:0 are
assumed to be 000_0000h for the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming address is less than the
value programmed in this register and greater than or equal to 4 GB.
BIOS Restriction: Minimum value for TOUUD is 4 GB.
These bits are Intel TXT lockable.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:39
38:20
19:1
0
76
0/0/0/PCI
A8–AFh
0000000000000000h
RW-KL, RW-L
64 bits
00000000000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 00000h Uncore
RO 0h
RW-KL 0b Uncore
Processor Configuration Registers
Description
Reserved
TOUUD (TOUUD)
This register contains bits 38:20 of an address one byte above the
maximum DRAM memory above 4 GB that is usable by the
operating system. Configuration software must set this value to
TOM minus all ME stolen memory if reclaim is disabled. If reclaim is
enabled, this value must be set to reclaim limit 1 MB aligned since
reclaim limit + 1 byte is 1 MB aligned. Address bits 19:0 are
assumed to be 000_0000h for the purposes of address
comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value
programmed in this register and greater than 4 GB.
All the bits in this register are locked in Intel TXT mode.
Reserved
Lock (LOCK)
This bit will lock all writeable settings in this register, including
itself.
Datasheet, Volume 2