Pcicmd6-Pci Command Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.10.3 PCICMD6—PCI Command Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:11
10
9
8
7:7
6
5
4
3
144
0/6/0/PCI
4–5h
0000h
RW, RO
16 bits
00h
Reset RST/
Attr
Value PWR
RO 0h
RW 0b Uncore
RO 0b Uncore
RW 0b Uncore
RO 0h
RW 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
Processor Configuration Registers
Description
Reserved
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be de-
asserted when this bit is set.
This bit only affects interrupts generated by the device (PCI INTA
from a PME or Hot Plug event) controlled by this command register.
It does not affect upstream MSIs, upstream PCI INTA–INTD assert
and deassert messages.
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
SERR# Message Enable (SERRE)
Controls the root port's SERR# messaging. The processor
communicates the SERR# condition by sending an SERR message
to the PCH. This bit, when set, enables reporting of non-fatal and
fatal errors detected by the device to the Root Complex. Note that
errors are reported if enabled either through this bit or through the
PCI-Express specific bits in the Device Control register.
In addition, for Type 1 configuration space header devices, this bit,
when set, enables transmission by the primary interface of
ERR_NONFATAL and ERR_FATAL error messages forwarded from
the secondary interface. This bit does not affect the transmission of
forwarded ERR_COR messages.
0 = The SERR message is generated by the root port only under
conditions enabled individually through the Device Control
register.
1 = The root port is enabled to generate SERR messages that will
be sent to the PCH for specific root port error conditions
generated/detected or received on the secondary side of the
virtual PCI-to-PCI bridge. The status of SERRs generated is
reported in the PCISTS register.
Reserved
Parity Error Response Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in the PCI
Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be
set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0.
Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0.
Datasheet, Volume 2