B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
10:10
9:4
3:0
2.10.40
SLOTCAP—Slot Capabilities Register
PCI Express Slot related registers allow for the support of Hot Plug.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:19
18
17
174
0/6/0/PCI
B2–B3h
1001h
RW1C, RO-V, RO
16 bits
0h
Reset
RST/
Attr
Value
PWR
RO
0h
RO-V
00h
Uncore
RO-V
1h
Uncore
0/6/0/PCI
B4–B7h
00040000h
RW-O, RO
32 bits
Reset
RST/
Attr
Value
PWR
RW-O
0000h
Uncore
RO
1b
Uncore
RO
0b
Uncore
Processor Configuration Registers
Description
Reserved
Negotiated Link Width (NLW)
This field indicates negotiated link width. This field is valid only
when the link is in the L0, L0s, or L1 states (after link width
negotiation is successfully completed).
00h = Reserved
01h = X1
02h = X2
04h = X4
08h = X8
10h = X16
All other encodings are reserved.
Current Link Speed (CLS)
This field indicates the negotiated Link speed of the given PCI
Express Link.
0001b = 2.5 GT/s PCI Express Link
0010b = 5.0 GT/s PCI Express Link
All other encodings are reserved.
The value in this field is undefined when the Link is not up.
Description
Physical Slot Number (PSN)
This field indicates the physical slot number attached to this Port.
BIOS Requirement: This field must be initialized by BIOS to a
value that assigns a slot number that is globally unique within the
chassis.
No Command Completed Support (NCCS)
When set to 1b, this bit indicates that this slot does not generate
software notification when an issued command is completed by the
Hot-Plug Controller. This bit is only permitted to be set to 1b if the
hotplug capable port is able to accept writes to all fields of the Slot
Control register without delay between successive writes.
Reserved for Electromechanical Interlock Present (EIP)
When set to 1b, this bit indicates that an Electromechanical
Interlock is implemented on the chassis for this slot.
Datasheet, Volume 2
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