Ver_Reg-Version Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Table 2-20. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 2 of
2)
Address
Offset
A8–ABhh
AC–AFh
B0–B7h
B8–BFh
C0–FFh
100–107h
108–10Fh
110–1FFh
200–207h
208–20Fh
210–FEFh
FF0–FF3h
2.18.1 VER_REG—Version Register
This register reports the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load
remapping hardware drivers written for prior architecture versions.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:8
7:4
3:0
216
Register
Symbol
IEADDR_REG Invalidation Event Address Register
IEUADDR_REG Invalidation Event Upper Address Register
RSVD Reserved
Interrupt Remapping Table Address Register
IRTA_REG
RSVD Reserved
Invalidate Address Register
IVA_REG
IOTLB Invalidate Register
IOTLB_REG
RSVD Reserved
Fault Recording Low Register
FRCDL_REG
Fault Recording High Register
FRCDH_REG
RSVD Reserved
DMA Remap Engine Policy Control
VTPOLICY
0/0/0/GFXVTBAR
0–3h
00000010h
RO
32 bits
000000h
Reset RST/
Attr
Value PWR
RO 0h
RO 0001b Uncore
RO 0000b Uncore
Processor Configuration Registers
Register Name
Description
Reserved
Major Version number (MAX)
This field indicates supported architecture version.
Minor Version number (MIN)
This field indicates supported architecture minor version.
Reset Value Access
00000000h RW-L
00000000h RW-L
0h RO
0000000000
RW-L
000000h
0h RO
0000000000
RW
000000h
0200000000 RW-V, RW,
000000h RO-V
0h RO
0000000000
ROS-V
000000h
0000000000 RO, RW1CS,
000000h ROS-V
0h RO
RO, RO-KFW,
00000000h
RW-KL, RW-L
Datasheet, Volume 2