Pci Express Lanes Connection; Direct Media Interface (Dmi); Dmi Error Flow; Processor/Pch Compatibility Assumptions - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

2.2.4

PCI Express Lanes Connection

Figure 2-5
Figure 2-5.

PCIe Typical Operation 16 lanes Mapping

2.3

Direct Media Interface (DMI)

Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported. The DMI is similar to a four-lane PCI Express supporting up to
1 GB/s of bandwidth in each direction.
Note: Only DMI x4 configuration is supported.
2.3.1

DMI Error Flow

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2

Processor/PCH Compatibility Assumptions

The processor is compatible with the
compatible with any previous PCH products.
30
demonstrates the PCIe lanes mapping.
0
1
2
3
Lane 0
0
Lane 1
1
Lane 2
2
Lane 3
3
Lane 4
4
Lane 5
5
Lane 6
6
Lane 7
7
Lane 8
0 8
Lane 9
1 9
Lane 10
2 10
Lane 11
3 11
Lane 12
4 12
Lane 13
5 13
Lane 14
6 14
Lane 15
7 15
®
I ntel 6 Series Chipset
Interfaces
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCH. The processor is not
Datasheet, Volume 1